root/loader/g7x2/main.c

DEFINITIONS

1. get_core_id
2. my_restart

   1 #include "../generic/check_compat.c"
   3 extern long *blob_chdk_core;
   4 extern long blob_chdk_core_size;
   6 int __attribute__((naked)) get_core_id() {
   7     asm volatile (
   8 "    mrc     p15, #0, r0, c0, c0, #5\n"
   9 "    ands    r0, #0xf\n"
  10 "    bx      lr\n"
  11     );
  12 }
  14 void __attribute__((noreturn)) my_restart()
  15 {
  16     int coreid = get_core_id();
  18     if (!coreid) {
check_compat();
  21         long *dst = (long*)MEMISOSTART;
  22         const long *src = blob_chdk_core;
  23         long length = (blob_chdk_core_size + 3) >> 2;
core_copy(src, dst, length);
  27         // GPIO base = 0xD2080000
  28         // 0xD20801E4   - SD led
  30         // light up green LED
  31         volatile int* p = (int*)0xD20801E4;
  32         *p = 0x24D0002;
  33     }
  35     asm volatile (
  36             "movs   r0, %2\n"
  37             "bne    cont1\n"
  39             "ldr    r2, =0xb5102101\n"  // First 2 instructions of function to call
  40             "ldr    r1, =0xe051e078\n"  // FW 1.10b
  41             "ldr    r0, [r1]\n"
  42             "cmp    r0, r2\n"           // instruction match?
  43             "beq    cont2\n"
  44             "ldr    r1, =0xe051e07c\n"  // FW 1.01a & 1.01b
  45         "cont2:\n"
  46             "orr    r1, #1\n"
  47             "movs   r0, #1\n"
  48             "blx    r1\n" // unblock core1
  50         "cont1:\n"
  51             "mov    r1, %1\n"
  52             "mov    r0, %0\n"
  53             "ldr    r2, =0xe042eb75\n" // address is OK for 101a
  54             "blx    r2\n"              // caching related routine called at fw startup
  55             "mov    r1, %1\n"
  56             "mov    r0, %0\n"
  57             "ldr    r2, =0xe042ec4d\n" // address is OK for 101a
  58             "blx    r2\n"              // caching related routine called at fw startup
  59             "mov    r0, %0\n"
  60             "add    r0, r0, #1\n"
  61             "bx     r0\n"
  62             : : "r"(MEMISOSTART), "r"(((blob_chdk_core_size+3)>>2)<<2), "r"(coreid) : "memory","r0","r1","r2","r3"
  63     );
  64     while(1);
  65 }