root/modules/cpuinfo_v7.c

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DEFINITIONS

This source file includes following definitions.
  1. two_on_nth
  2. two_on_nth_granule
  3. ctype_str
  4. ccsidr_linesize
  5. ccsidr_plusone
  6. cache_tcm_size_str
  7. cache_tcm_addr_str
  8. mpu_region_size_str
  9. bitfield8
  10. mpu_rattr
  11. dbg_version
  12. cpuinfo_get_info

   1 // cpuinfo, ARMv7 specific parts
   2 
   3 static char linebuf[128]; // fixed buffer for outputting dynamic strings from interpreter functions
   4 
   5 static const char *two_nth_str[] = {
   6 "1", "2", "4", "8", "16", "32", "64", "128", "256", "512", "1K", "2K", "4K", "8K", "16K", "32K"
   7 };
   8 
   9 static const char *two_on_nth(unsigned val) {
  10     if (val < 16) {
  11         return two_nth_str[val];
  12     }
  13     return "invalid";
  14 }
  15 
  16 static const char *two_on_nth_granule(unsigned val) {
  17     if (val == 0) {
  18         return "no info";
  19     }
  20     else if (val > 9) {
  21         return "reserved";
  22     }
  23     else {
  24         return two_nth_str[val];
  25     }
  26     return "invalid";
  27 }
  28 
  29 const struct cpuinfo_bitfield_desc_s cpuinf_feat0[] = {
  30     {4,"ARM inst set"},
  31     {4,"Thumb inst set"},
  32     {4,"Jazelle inst set"},
  33     {4,"ThumbEE inst set"},
  34     {16,"-"},
  35     {}
  36 };
  37 
  38 const struct cpuinfo_bitfield_desc_s cpuinf_feat1[] = {
  39     {4,"Programmers' model"},
  40     {4,"Security extensions"},
  41     {4,"Microcontr. prog model"},
  42     {20,"-"},
  43     {}
  44 };
  45 
  46 const struct cpuinfo_bitfield_desc_s cpuinf_mmfr0[] = {
  47     {4,"VMSA support"},
  48     {4,"PMSA support"},
  49     {4,"Cache coherence"},
  50     {4,"Outer shareable"},
  51     {4,"TCM support"},
  52     {4,"Auxiliary registers"},
  53     {4,"FCSE support"},
  54     {4,"-"},
  55     {}
  56 };
  57 
  58 const struct cpuinfo_bitfield_desc_s cpuinf_mmfr1[] = {
  59     {4,"L1 Harvard cache VA"},
  60     {4,"L1 unified cache VA"},
  61     {4,"L1 Harvard cache s/w"},
  62     {4,"L1 unified cache s/w"},
  63     {4,"L1 Harvard cache"},
  64     {4,"L1 unified cache"},
  65     {4,"L1 cache test & clean"},
  66     {4,"Branch predictor"},
  67     {}
  68 };
  69 
  70 const struct cpuinfo_bitfield_desc_s cpuinf_mmfr2[] = {
  71     {4,"L1 Harvard fg prefetch"},
  72     {4,"L1 Harvard bg prefetch"},
  73     {4,"L1 Harvard range"},
  74     {4,"Harvard TLB"},
  75     {4,"Unified TLB"},
  76     {4,"Mem barrier"},
  77     {4,"WFI stall"},
  78     {4,"HW access flag"},
  79     {}
  80 };
  81 
  82 const struct cpuinfo_bitfield_desc_s cpuinf_mmfr3[] = {
  83     {4,"Cache maintain MVA"},
  84     {4,"Cache maintain s/w"},
  85     {4,"BP maintain"},
  86     {16,"-"},
  87     {4,"Supersection support"},
  88     {}
  89 };
  90 
  91 const struct cpuinfo_bitfield_desc_s cpuinf_isar0[] = {
  92     {4,"Swap instrs"},
  93     {4,"Bitcount instrs"},
  94     {4,"Bitfield instrs"},
  95     {4,"CmpBranch instrs"},
  96     {4,"Coproc instrs"},
  97     {4,"Debug instrs"},
  98     {4,"Divide instrs"},
  99     {4,"-"},
 100     {}
 101 };
 102 
 103 const struct cpuinfo_bitfield_desc_s cpuinf_isar1[] = {
 104     {4,"Endian instrs"},
 105     {4,"Exception instrs"},
 106     {4,"Exception AR instrs"},
 107     {4,"Extend instrs"},
 108     {4,"IfThen instrs"},
 109     {4,"Immediate instrs"},
 110     {4,"Interwork instrs"},
 111     {4,"Jazelle instrs"},
 112     {}
 113 };
 114 
 115 const struct cpuinfo_bitfield_desc_s cpuinf_isar2[] = {
 116     {4,"LoadStore instrs"},
 117     {4,"Memhint instrs"},
 118     {4,"MultiAccess Interruptible instructions"},
 119     {4,"Mult instrs"},
 120     {4,"MultS instrs"},
 121     {4,"MultU instrs"},
 122     {4,"PSR AR instrs"},
 123     {4,"Reversal instrs"},
 124     {}
 125 };
 126 
 127 const struct cpuinfo_bitfield_desc_s cpuinf_isar3[] = {
 128     {4,"Saturate instrs"},
 129     {4,"SIMD instrs"},
 130     {4,"SVC instrs"},
 131     {4,"SynchPrim instrs"},
 132     {4,"TabBranch instrs"},
 133     {4,"ThumbCopy instrs"},
 134     {4,"TrueNOP instrs"},
 135     {4,"T2 Exec Env instrs"},
 136     {}
 137 };
 138 
 139 const struct cpuinfo_bitfield_desc_s cpuinf_isar4[] = {
 140     {4,"Unprivileged instrs"},
 141     {4,"WithShifts instrs"},
 142     {4,"Writeback instrs"},
 143     {4,"SMC instrs"},
 144     {4,"Barrier instrs"},
 145     {4,"SynchPrim_instrs_frac"},
 146     {4,"PSR_M instrs"},
 147     {4,"-"},
 148     {}
 149 };
 150 
 151 const struct cpuinfo_bitfield_desc_s cpuinf_isar5[] = {
 152     {32,"-"},
 153     {}
 154 };
 155 
 156 const struct cpuinfo_bitfield_desc_s cpuinf_ctr[] = {
 157     {4,"Icache min words/line", two_on_nth},
 158     {10,"(zero)"},
 159     {2,"L1 Icache policy"},
 160     {4,"Dcache min words/line", two_on_nth},
 161     {4,"Exclusives Reservation Granule", two_on_nth_granule},
 162     {4,"Cache Writeback Granule", two_on_nth_granule},
 163     {1,"(zero)"},
 164     {3,"(register format)"},
 165     {}
 166 };
 167 
 168 static const char *ctype_str(unsigned val) {
 169     switch (val) {
 170         case 0: return "no cache";
 171         case 1: return "Icache only";
 172         case 2: return "Dcache only";
 173         case 3: return "Separate Icache, Dcache";
 174         case 4: return "Unified cache";
 175     }
 176     return "-";
 177 }
 178 
 179 const struct cpuinfo_bitfield_desc_s cpuinf_clidr[] = {
 180     {3,"Cache type, level1", ctype_str},
 181     {3,"Cache type, level2", ctype_str},
 182     {3,"Cache type, level3", ctype_str},
 183     {3,"Cache type, level4", ctype_str},
 184     {3,"Cache type, level5", ctype_str},
 185     {3,"Cache type, level6", ctype_str},
 186     {3,"Cache type, level7", ctype_str},
 187     {3,"Cache type, level8", ctype_str},
 188     {3,"Level of coherency"},
 189     {3,"Level of unification"},
 190     {2,"(zero)"},
 191     {}
 192 };
 193 
 194 const struct cpuinfo_bitfield_desc_s cpuinf_csselr[] = {
 195     {1,"Instruction, not data"},
 196     {3,"Level"},
 197     {28,"(unknown)"},
 198     {}
 199 };
 200 
 201 static const char *ccsidr_linesize(unsigned val) {
 202     return two_nth_str[val+2];
 203 }
 204 
 205 static const char *ccsidr_plusone(unsigned val) {
 206     sprintf(linebuf,"%i",val+1);
 207     return linebuf;
 208 }
 209 
 210 const struct cpuinfo_bitfield_desc_s cpuinf_ccsidr[] = {
 211     {3,"Line size in words", ccsidr_linesize},
 212     {10,"Associativity", ccsidr_plusone},
 213     {15,"Number of sets", ccsidr_plusone},
 214     {1,"Write allocation"},
 215     {1,"Read allocation"},
 216     {1,"Write back"},
 217     {1,"Write through"},
 218     {}
 219 };
 220 
 221 static const char *cache_tcm_size_str(unsigned val) {
 222     if (val == 0) 
 223         return "0";
 224     if (val < 3 || val > 14)
 225         return "invalid";
 226     return reg_sizes[val-3];
 227 }
 228 
 229 static const char *cache_tcm_addr_str(unsigned val) {
 230     sprintf(linebuf,"0x%08x",val<<12);
 231     return linebuf;
 232 }
 233 
 234 const struct cpuinfo_bitfield_desc_s cpuinf_tcmreg[] = {
 235     {1,"Enabled"},
 236     {1,"-"},
 237     {5,"Size", cache_tcm_size_str},
 238     {5,"-"},
 239     {20,"Base address", cache_tcm_addr_str},
 240     {}
 241 };
 242 
 243 const struct cpuinfo_bitfield_desc_s cpuinf_mputype[] = {
 244     {1,"S"},
 245     {7,"-"},
 246     {8,"Num of MPU regions"},
 247     {}
 248 };
 249 
 250 const struct cpuinfo_bitfield_desc_s cpuinf_mpubase[] = {
 251     {32,"Base address"},
 252     {}
 253 };
 254 
 255 const struct cpuinfo_bitfield_desc_s cpuinf_sctlr[] = {
 256     {1,"MPU Enable"},
 257     {1,"Strict Align"},
 258     {1,"L1 DCache Enable"},
 259     {4,"- (SBO)"},
 260     {4,"- (SBZ)"},
 261     {1,"Branch Pred Enable"},
 262     {1,"L1 ICache Enable"},
 263     {1,"High Vector"},
 264     {1,"Round Robin"},
 265     {1,"- (SBZ)"},
 266     {1,"- (SBO)"},
 267     {1,"MPU background reg"},
 268     {1,"- (SBO)"},
 269     {1,"Div0 exception"},
 270     {1,"- (SBZ)"},
 271     {1,"FIQ Enable"},
 272     {2,"- (SBO)"},
 273     {1,"VIC"},
 274     {1,"CPSR E bit"},
 275     {1,"- (SBZ)"},
 276     {1,"NMFI"},
 277     {1,"TRE"},
 278     {1,"AFE"},
 279     {1,"Thumb exceptions"},
 280     {1,"Endian"},
 281     {}
 282 };
 283 
 284 static const char *mpu_region_size_str(unsigned val) {
 285     if (val < 4 || val > 31)
 286         return "invalid";
 287     if (val < 11)
 288         return two_nth_str[val+1];
 289     return reg_sizes[val-11];
 290 }
 291 
 292 static const char *bitfield8(unsigned val) {
 293     linebuf[8] = 0;
 294     int n;
 295     for (n=0; n<8; n++) {
 296         linebuf[7-n] = (val & (1<<n))?'1':'0';
 297     }
 298     return linebuf;
 299 }
 300 
 301 const struct cpuinfo_bitfield_desc_s cpuinf_mpusizeen[] = {
 302     {1,"Enabled"},
 303     {5,"Size", mpu_region_size_str},
 304     {2,"-"},
 305     {8,"Sub-regions disabled", bitfield8},
 306     {}
 307 };
 308 
 309 static const char *mpu_rattr(unsigned val) {
 310     char *s="";
 311     char *s2="";
 312     char *t;
 313     t = (val&4)?"Shared":"Non-shared";
 314     if (val&0x20) {
 315         switch (val&3) {
 316             case 0: s = "Inner Non-cacheable"; break;
 317             case 1: s = "Inner Write-back, write-allocate"; break;
 318             case 2: s = "Inner Write-through, no write-allocate"; break;
 319             case 3: s = "Inner Write-back, no write-allocate"; break;
 320         }
 321         switch ((val&0x18)>>3) {
 322             case 0: s2 = "Outer Non-cacheable"; break;
 323             case 1: s2 = "Outer Write-back, write-allocate"; break;
 324             case 2: s2 = "Outer Write-through, no write-allocate"; break;
 325             case 3: s2 = "Outer Write-back, no write-allocate"; break;
 326         }
 327         sprintf(linebuf,"%s; %s; %s",s, s2, t);
 328     }
 329     else {
 330         switch (val&0x1B) {
 331             case 0: s = "Strongly ordered, shareable"; t=""; break;
 332             case 1: s = "Shareable device"; t="Shareable"; break;
 333             case 2: s = "Outer and Inner write-through, no write-allocate"; break;
 334             case 3: s = "Outer and Inner write-back, no write-allocate"; break;
 335             case 8: s = "Outer and Inner Non-cacheable"; break;
 336             case 11: s = "Outer and Inner write-back, write-allocate"; break;
 337             case 16: s = "Non-shareable Device"; t=""; break;
 338             default: s = "(reserved)"; t="";
 339         }
 340         sprintf(linebuf,"%s; %s",s, t);
 341     }
 342     return linebuf;
 343 }
 344 
 345 const struct cpuinfo_bitfield_desc_s cpuinf_accesscontrol[] = {
 346     {6,"Region attributes", mpu_rattr},
 347     {2,"-"},
 348     {3,"Access permission", regperm_str},
 349     {1,"-"},
 350     {1,"Execute never"},
 351     {}
 352 };
 353 
 354 const struct cpuinfo_bitfield_desc_s cpuinf_generic[] = {
 355     {32,"(raw value)"},
 356     {}
 357 };
 358 
 359 static const char * dbg_version(unsigned val) {
 360     switch(val) {
 361         case 0b0001: return "v6";
 362         case 0b0010: return "v6.1";
 363         case 0b0011: return "v7 full";
 364         case 0b0100: return "v7 basic";
 365         case 0b0101: return "v7.1";
 366         case 0b0110: return "v8";
 367         case 0b0111: return "v8.1";
 368         case 0b1000: return "v8.2";
 369     }
 370     return "???";
 371 }
 372 
 373 static const struct cpuinfo_bitfield_desc_s cpuinf_dbgdidr[] = {
 374     {4,"Revision"},
 375     {4,"Variant"},
 376     {8,"- (RAZ)"},
 377     {4,"Version",dbg_version},
 378     {4,"Context",ccsidr_plusone},
 379     {4,"BRP",ccsidr_plusone},
 380     {4,"WRP",ccsidr_plusone},
 381     {}
 382 };
 383 
 384 static const struct cpuinfo_bitfield_desc_s cpuinf_dbgd_address[] = {
 385     {2,"Valid"},
 386     {10,"- (UNK)"},
 387     {20,"Address",cache_tcm_addr_str},
 388     {}
 389 };
 390 
 391 static const struct cpuinfo_bitfield_desc_s cpuinf_dbgdscr[] = {
 392     {1,"HALTED"},
 393     {1,"RESTARTED"},
 394     {4,"MOE"},
 395     {1,"SDABORT_l"},
 396     {1,"ADABORT_l"},
 397     {1,"UND_l"},
 398     {1,"FS"},
 399     {1,"DBGack"},
 400     {1,"INTdis"},
 401     {1,"UDCCdis"},
 402     {1,"ITRen"},
 403     {1,"HDBGen"},
 404     {1,"MDBGen"},
 405     {1,"SPIDdis"},
 406     {1,"SPNIDdis"},
 407     {1,"NS"},
 408     {1,"ADAdiscard"},
 409     {2,"ExtDCCmode"},
 410     {2,"- (SBZ)"},
 411     {1,"InstrCompl_l"},
 412     {1,"PipeAdv"},
 413     {1,"TXfull_l"},
 414     {1,"RXfull_l"},
 415     {1,"- (SBZ)"},
 416     {1,"TXfull"},
 417     {1,"RXfull"},
 418     {1,"- (SBZ)"},
 419     {}
 420 };
 421 
 422 const struct cpuinfo_word_desc_s cpuinfo_desc[]={
 423     {"ID", cpuinf_id },
 424     {"Cache type", cpuinf_ctr },
 425     {"TCM type", cpuinf_generic },
 426     {"MPU type", cpuinf_mputype },
 427     {"Multiprocessor ID", cpuinf_generic },
 428     {"Processor feature 0", cpuinf_feat0 },
 429     {"Processor feature 1", cpuinf_feat1 },
 430     {"Debug feature", cpuinf_generic },
 431     {"Aux feature", cpuinf_generic },
 432     {"Mem model feature 0", cpuinf_mmfr0 },
 433     {"Mem model feature 1", cpuinf_mmfr1 },
 434     {"Mem model feature 2", cpuinf_mmfr2 },
 435     {"Mem model feature 3", cpuinf_mmfr3 },
 436     {"ISA feature 0", cpuinf_isar0 },
 437     {"ISA feature 1", cpuinf_isar1 },
 438     {"ISA feature 2", cpuinf_isar2 },
 439     {"ISA feature 3", cpuinf_isar3 },
 440     {"ISA feature 4", cpuinf_isar4 },
 441     {"ISA feature 5", cpuinf_isar5 },
 442     {"Cache level ID", cpuinf_clidr },
 443     {"Cache size ID reg (data, level0)", cpuinf_ccsidr },
 444     {"Cache size ID reg (inst, level0)", cpuinf_ccsidr },
 445     {"SCTLR", cpuinf_sctlr },
 446     {"ACTLR", cpuinf_generic },
 447     {"ACTLR2", cpuinf_generic },
 448     {"CPACR", cpuinf_generic },
 449     {"Build options 1", cpuinf_generic },
 450     {"Build options 2", cpuinf_generic },
 451     {"ATCM region reg", cpuinf_tcmreg },
 452     {"BTCM region reg", cpuinf_tcmreg },
 453     {"MPU region 0 base", cpuinf_mpubase },
 454     {"MPU region 0 size & enable", cpuinf_mpusizeen },
 455     {"MPU region 0 access control", cpuinf_accesscontrol },
 456     {"MPU region 1 base", cpuinf_mpubase },
 457     {"MPU region 1 size & enable", cpuinf_mpusizeen },
 458     {"MPU region 1 access control", cpuinf_accesscontrol },
 459     {"MPU region 2 base", cpuinf_mpubase },
 460     {"MPU region 2 size & enable", cpuinf_mpusizeen },
 461     {"MPU region 2 access control", cpuinf_accesscontrol },
 462     {"MPU region 3 base", cpuinf_mpubase },
 463     {"MPU region 3 size & enable", cpuinf_mpusizeen },
 464     {"MPU region 3 access control", cpuinf_accesscontrol },
 465     {"MPU region 4 base", cpuinf_mpubase },
 466     {"MPU region 4 size & enable", cpuinf_mpusizeen },
 467     {"MPU region 4 access control", cpuinf_accesscontrol },
 468     {"MPU region 5 base", cpuinf_mpubase },
 469     {"MPU region 5 size & enable", cpuinf_mpusizeen },
 470     {"MPU region 5 access control", cpuinf_accesscontrol },
 471     {"MPU region 6 base", cpuinf_mpubase },
 472     {"MPU region 6 size & enable", cpuinf_mpusizeen },
 473     {"MPU region 6 access control", cpuinf_accesscontrol },
 474     {"MPU region 7 base", cpuinf_mpubase },
 475     {"MPU region 7 size & enable", cpuinf_mpusizeen },
 476     {"MPU region 7 access control", cpuinf_accesscontrol },
 477     //{"Floating Point System ID register", cpuinf_generic },
 478     //{"Media and VFP Feature Register 0", cpuinf_generic },
 479     //{"Media and VFP Feature Register 1", cpuinf_generic },
 480     {"DBGDIDR", cpuinf_dbgdidr },
 481     {"DBGDRAR", cpuinf_dbgd_address },
 482     {"DBGDSAR", cpuinf_dbgd_address },
 483     {"DBGDSCR", cpuinf_dbgdscr },
 484     {}
 485 };
 486 
 487 
 488 void __attribute__((naked,noinline)) cpuinfo_get_info(unsigned *results) {
 489     asm (
 490         ".syntax unified\n"
 491         ".code 16\n"
 492         ".align 2\n"
 493         "BX      PC\n"                  // switch to ARM mode
 494         ".code 32\n"
 495 
 496         "MRC    p15, 0, R1,c0,c0\n" // ident
 497         "STR    R1, [R0]\n"
 498 
 499         "MRC    p15, 0, R1,c0,c0,1\n" // cache
 500         "ADD    R0, R0, #4\n"
 501         "STR    R1, [R0]\n"
 502 
 503         "MRC    p15, 0, R1,c0,c0,2\n" // TCM
 504         "ADD    R0, R0, #4\n"
 505         "STR    R1, [R0]\n"
 506 
 507         "MRC    p15, 0, R1,c0,c0,4\n" // MPU
 508         "ADD    R0, R0, #4\n"
 509         "STR    R1, [R0]\n"
 510 
 511         "MRC    p15, 0, R1,c0,c0,5\n" // MPIDR
 512         "ADD    R0, R0, #4\n"
 513         "STR    R1, [R0]\n"
 514 
 515         "MRC    p15, 0, R1,c0,c1,0\n" // ID_PFR0
 516         "ADD    R0, R0, #4\n"
 517         "STR    R1, [R0]\n"
 518 
 519         "MRC    p15, 0, R1,c0,c1,1\n" // ID_PFR1
 520         "ADD    R0, R0, #4\n"
 521         "STR    R1, [R0]\n"
 522 
 523         "MRC    p15, 0, R1,c0,c1,2\n" // ID_DFR0
 524         "ADD    R0, R0, #4\n"
 525         "STR    R1, [R0]\n"
 526 
 527         "MRC    p15, 0, R1,c0,c1,3\n" // ID_AFR0
 528         "ADD    R0, R0, #4\n"
 529         "STR    R1, [R0]\n"
 530 
 531         "MRC    p15, 0, R1,c0,c1,4\n" // ID_MMFR0
 532         "ADD    R0, R0, #4\n"
 533         "STR    R1, [R0]\n"
 534 
 535         "MRC    p15, 0, R1,c0,c1,5\n" // ID_MMFR1
 536         "ADD    R0, R0, #4\n"
 537         "STR    R1, [R0]\n"
 538 
 539         "MRC    p15, 0, R1,c0,c1,6\n" // ID_MMFR2
 540         "ADD    R0, R0, #4\n"
 541         "STR    R1, [R0]\n"
 542 
 543         "MRC    p15, 0, R1,c0,c1,7\n" // ID_MMFR3
 544         "ADD    R0, R0, #4\n"
 545         "STR    R1, [R0]\n"
 546 
 547         "MRC    p15, 0, R1,c0,c2,0\n" // ID_ISAR0
 548         "ADD    R0, R0, #4\n"
 549         "STR    R1, [R0]\n"
 550 
 551         "MRC    p15, 0, R1,c0,c2,1\n" // ID_ISAR1
 552         "ADD    R0, R0, #4\n"
 553         "STR    R1, [R0]\n"
 554 
 555         "MRC    p15, 0, R1,c0,c2,2\n" // ID_ISAR2
 556         "ADD    R0, R0, #4\n"
 557         "STR    R1, [R0]\n"
 558 
 559         "MRC    p15, 0, R1,c0,c2,3\n" // ID_ISAR3
 560         "ADD    R0, R0, #4\n"
 561         "STR    R1, [R0]\n"
 562 
 563         "MRC    p15, 0, R1,c0,c2,4\n" // ID_ISAR4
 564         "ADD    R0, R0, #4\n"
 565         "STR    R1, [R0]\n"
 566 
 567         "MRC    p15, 0, R1,c0,c2,5\n" // ID_ISAR5
 568         "ADD    R0, R0, #4\n"
 569         "STR    R1, [R0]\n"
 570 
 571         "MRC    p15, 1, R1,c0,c0,1\n" // CLIDR
 572         "ADD    R0, R0, #4\n"
 573         "STR    R1, [R0]\n"
 574 
 575         "MOV    R1, #0\n"
 576         "MCR    p15, 2, R1,c0,c0,0\n" // CSSELR (data cache, level0)
 577 
 578         "MRC    p15, 1, R1,c0,c0,0\n" // CCSIDR (the currently selected one)
 579         "ADD    R0, R0, #4\n"
 580         "STR    R1, [R0]\n"
 581 
 582         "MOV    R1, #1\n"
 583         "MCR    p15, 2, R1,c0,c0,0\n" // CSSELR (inst cache, level0)
 584 
 585         "MRC    p15, 1, R1,c0,c0,0\n" // CCSIDR (the currently selected one)
 586         "ADD    R0, R0, #4\n"
 587         "STR    R1, [R0]\n"
 588 
 589         "MRC    p15, 0, R1,c1,c0,0\n" // SCTLR
 590         "ADD    R0, R0, #4\n"
 591         "STR    R1, [R0]\n"
 592 
 593         "MRC    p15, 0, R1,c1,c0,1\n" // ACTLR
 594         "ADD    R0, R0, #4\n"
 595         "STR    R1, [R0]\n"
 596 
 597 //#ifndef CONFIG_QEMU
 598         "MRC    p15, 0, R1,c15,c0,0\n" // ACTLR2
 599         "ADD    R0, R0, #4\n"
 600         "STR    R1, [R0]\n"
 601 //#endif
 602 
 603         "MRC    p15, 0, R1,c1,c0,2\n" // CPACR
 604         "ADD    R0, R0, #4\n"
 605         "STR    R1, [R0]\n"
 606 
 607         "MRC    p15, 0, R1,c15,c2,0\n" // Build options 1 reg
 608         "ADD    R0, R0, #4\n"
 609         "STR    R1, [R0]\n"
 610 
 611         "MRC    p15, 0, R1,c15,c2,1\n" // Build options 2 reg
 612         "ADD    R0, R0, #4\n"
 613         "STR    R1, [R0]\n"
 614 
 615         "MRC    p15, 0, R1,c9,c1,1\n" // ATCM region reg
 616         "ADD    R0, R0, #4\n"
 617         "STR    R1, [R0]\n"
 618 
 619         "MRC    p15, 0, R1,c9,c1,0\n" // BTCM region reg
 620         "ADD    R0, R0, #4\n"
 621         "STR    R1, [R0]\n"
 622 
 623         "MOV    R1, #0\n"
 624         "MCR    p15, 0, R1,c6,c2,0\n" // MPU Memory Region Number Register, region 0
 625 
 626         "MRC    p15, 0, R1,c6,c1,0\n" // MPU region base register
 627         "ADD    R0, R0, #4\n"
 628         "STR    R1, [R0]\n"
 629         "MRC    p15, 0, R1,c6,c1,2\n" // MPU Region Size and Enable Register
 630         "ADD    R0, R0, #4\n"
 631         "STR    R1, [R0]\n"
 632         "MRC    p15, 0, R1,c6,c1,4\n" // MPU Region Access Control Register
 633         "ADD    R0, R0, #4\n"
 634         "STR    R1, [R0]\n"
 635 
 636         "MOV    R1, #1\n"
 637         "MCR    p15, 0, R1,c6,c2,0\n" // region 1
 638 
 639         "MRC    p15, 0, R1,c6,c1,0\n" // MPU region base register
 640         "ADD    R0, R0, #4\n"
 641         "STR    R1, [R0]\n"
 642         "MRC    p15, 0, R1,c6,c1,2\n" // MPU Region Size and Enable Register
 643         "ADD    R0, R0, #4\n"
 644         "STR    R1, [R0]\n"
 645         "MRC    p15, 0, R1,c6,c1,4\n" // MPU Region Access Control Register
 646         "ADD    R0, R0, #4\n"
 647         "STR    R1, [R0]\n"
 648 
 649         "MOV    R1, #2\n"
 650         "MCR    p15, 0, R1,c6,c2,0\n" // region 2
 651 
 652         "MRC    p15, 0, R1,c6,c1,0\n" // MPU region base register
 653         "ADD    R0, R0, #4\n"
 654         "STR    R1, [R0]\n"
 655         "MRC    p15, 0, R1,c6,c1,2\n" // MPU Region Size and Enable Register
 656         "ADD    R0, R0, #4\n"
 657         "STR    R1, [R0]\n"
 658         "MRC    p15, 0, R1,c6,c1,4\n" // MPU Region Access Control Register
 659         "ADD    R0, R0, #4\n"
 660         "STR    R1, [R0]\n"
 661 
 662         "MOV    R1, #3\n"
 663         "MCR    p15, 0, R1,c6,c2,0\n" // region 3
 664 
 665         "MRC    p15, 0, R1,c6,c1,0\n" // MPU region base register
 666         "ADD    R0, R0, #4\n"
 667         "STR    R1, [R0]\n"
 668         "MRC    p15, 0, R1,c6,c1,2\n" // MPU Region Size and Enable Register
 669         "ADD    R0, R0, #4\n"
 670         "STR    R1, [R0]\n"
 671         "MRC    p15, 0, R1,c6,c1,4\n" // MPU Region Access Control Register
 672         "ADD    R0, R0, #4\n"
 673         "STR    R1, [R0]\n"
 674 
 675         "MOV    R1, #4\n"
 676         "MCR    p15, 0, R1,c6,c2,0\n" // region 4
 677 
 678         "MRC    p15, 0, R1,c6,c1,0\n" // MPU region base register
 679         "ADD    R0, R0, #4\n"
 680         "STR    R1, [R0]\n"
 681         "MRC    p15, 0, R1,c6,c1,2\n" // MPU Region Size and Enable Register
 682         "ADD    R0, R0, #4\n"
 683         "STR    R1, [R0]\n"
 684         "MRC    p15, 0, R1,c6,c1,4\n" // MPU Region Access Control Register
 685         "ADD    R0, R0, #4\n"
 686         "STR    R1, [R0]\n"
 687 
 688         "MOV    R1, #5\n"
 689         "MCR    p15, 0, R1,c6,c2,0\n" // region 5
 690 
 691         "MRC    p15, 0, R1,c6,c1,0\n" // MPU region base register
 692         "ADD    R0, R0, #4\n"
 693         "STR    R1, [R0]\n"
 694         "MRC    p15, 0, R1,c6,c1,2\n" // MPU Region Size and Enable Register
 695         "ADD    R0, R0, #4\n"
 696         "STR    R1, [R0]\n"
 697         "MRC    p15, 0, R1,c6,c1,4\n" // MPU Region Access Control Register
 698         "ADD    R0, R0, #4\n"
 699         "STR    R1, [R0]\n"
 700 
 701         "MOV    R1, #6\n"
 702         "MCR    p15, 0, R1,c6,c2,0\n" // region 6
 703 
 704         "MRC    p15, 0, R1,c6,c1,0\n" // MPU region base register
 705         "ADD    R0, R0, #4\n"
 706         "STR    R1, [R0]\n"
 707         "MRC    p15, 0, R1,c6,c1,2\n" // MPU Region Size and Enable Register
 708         "ADD    R0, R0, #4\n"
 709         "STR    R1, [R0]\n"
 710         "MRC    p15, 0, R1,c6,c1,4\n" // MPU Region Access Control Register
 711         "ADD    R0, R0, #4\n"
 712         "STR    R1, [R0]\n"
 713 
 714         "MOV    R1, #7\n"
 715         "MCR    p15, 0, R1,c6,c2,0\n" // region 7
 716 
 717         "MRC    p15, 0, R1,c6,c1,0\n" // MPU region base register
 718         "ADD    R0, R0, #4\n"
 719         "STR    R1, [R0]\n"
 720         "MRC    p15, 0, R1,c6,c1,2\n" // MPU Region Size and Enable Register
 721         "ADD    R0, R0, #4\n"
 722         "STR    R1, [R0]\n"
 723         "MRC    p15, 0, R1,c6,c1,4\n" // MPU Region Access Control Register
 724         "ADD    R0, R0, #4\n"
 725         "STR    R1, [R0]\n"
 726 
 727         "MRC    p14, 0, R1,c0,c0,0\n" // DBGDIDR
 728         "ADD    R0, R0, #4\n"
 729         "STR    R1, [R0]\n"
 730 
 731         "MRC    p14, 0, R1,c1,c0,0\n" // DBGDRAR
 732         "ADD    R0, R0, #4\n"
 733         "STR    R1, [R0]\n"
 734 
 735         "MRC    p14, 0, R1,c2,c0,0\n" // DBGDSAR
 736         "ADD    R0, R0, #4\n"
 737         "STR    R1, [R0]\n"
 738 
 739         "MRC    p14, 0, R1,c0,c1,0\n" // DBGDSCR
 740         "ADD    R0, R0, #4\n"
 741         "STR    R1, [R0]\n"
 742 
 743         //".word  0xEEF01A10\n" //"VMRS   R1, FPSID\n" // Floating Point System ID register
 744         //"ADD    R0, R0, #4\n"
 745         //"STR    R1, [R0]\n"
 746 
 747         //".word  0xEEF71A10\n" //"VMRS   R1, MVFR0\n" // Media and VFP Feature Register 0
 748         //"ADD    R0, R0, #4\n"
 749         //"STR    R1, [R0]\n"
 750 
 751         //".word  0xEEF61A10\n" //"VMRS   R1, MVFR1\n" // Media and VFP Feature Register 1
 752         //"ADD    R0, R0, #4\n"
 753         //"STR    R1, [R0]\n"
 754 
 755         "BX     LR\n"
 756 
 757         :::"r0","r1"
 758     );
 759 }

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