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cpuinfo_v5.c-Dateireferenz
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Funktionen

static const char * cache_words_line_str (unsigned val)
 
static const char * cache_tcm_size_str (unsigned val)
 
static const char * protreg_size_str (unsigned val)
 
static const char * protreg_base_str (unsigned val)
 
static const char * tcmcfg_size_str (unsigned val)
 
void __attribute__ ((naked, noinline))
 

Variablen

struct cpuinfo_bitfield_desc_s cpuinf_cachetype []
 
struct cpuinfo_bitfield_desc_s cpuinf_tcmtype []
 
struct cpuinfo_bitfield_desc_s cpuinf_control []
 
struct cpuinfo_bitfield_desc_s cpuinf_regbits []
 
struct cpuinfo_bitfield_desc_s cpuinf_protreg []
 
struct cpuinfo_bitfield_desc_s cpuinf_regperms []
 
struct cpuinfo_bitfield_desc_s cpuinf_tcmcfg []
 
struct cpuinfo_word_desc_s cpuinfo_desc []
 

Dokumentation der Funktionen

void __attribute__ ( (naked, noinline)  )

Definiert in Zeile 155 der Datei cpuinfo_v5.c.

155  {
156  asm (
157  ".code 16\n"
158  ".align 2\n"
159  "BX PC\n" // switch to ARM mode
160  ".code 32\n"
161  "MRC p15, 0, R1,c0,c0\n" // ident
162  "STR R1, [R0]\n"
163  "MRC p15, 0, R1,c0,c0,1\n" // cache
164  "ADD R0, R0, #4\n"
165  "STR R1, [R0]\n"
166  "MRC p15, 0, R1,c0,c0,2\n" // TCM
167  "ADD R0, R0, #4\n"
168  "STR R1, [R0]\n"
169  "MRC p15, 0, R1,c1,c0\n" // control bits
170  "ADD R0, R0, #4\n"
171  "STR R1, [R0]\n"
172  "MRC p15, 0, R1,c6,c0\n" // protection region 0
173  "ADD R0, R0, #4\n"
174  "STR R1, [R0]\n"
175 
176  "MRC p15, 0, R1,c6,c1\n" // protection region 1
177  "ADD R0, R0, #4\n"
178  "STR R1, [R0]\n"
179 
180  "MRC p15, 0, R1,c6,c2\n" // protection region 2
181  "ADD R0, R0, #4\n"
182  "STR R1, [R0]\n"
183 
184  "MRC p15, 0, R1,c6,c3\n" // protection region 3
185  "ADD R0, R0, #4\n"
186  "STR R1, [R0]\n"
187 
188  "MRC p15, 0, R1,c6,c4\n" // protection region 4
189  "ADD R0, R0, #4\n"
190  "STR R1, [R0]\n"
191 
192  "MRC p15, 0, R1,c6,c5\n" // protection region 5
193  "ADD R0, R0, #4\n"
194  "STR R1, [R0]\n"
195 
196  "MRC p15, 0, R1,c6,c6\n" // protection region 6
197  "ADD R0, R0, #4\n"
198  "STR R1, [R0]\n"
199 
200  "MRC p15, 0, R1,c6,c7\n" // protection region 7
201  "ADD R0, R0, #4\n"
202  "STR R1, [R0]\n"
203 
204  "MRC p15, 0, R1,c5,c0,2\n" // data accesss perm
205  "ADD R0, R0, #4\n"
206  "STR R1, [R0]\n"
207 
208  "MRC p15, 0, R1,c5,c0,3\n" // instruction accesss perm
209  "ADD R0, R0, #4\n"
210  "STR R1, [R0]\n"
211 
212  "MRC p15, 0, R1,c2,c0\n" // data cache config
213  "ADD R0, R0, #4\n"
214  "STR R1, [R0]\n"
215  "MRC p15, 0, R1,c2,c0,1\n" // instruction cache config
216  "ADD R0, R0, #4\n"
217  "STR R1, [R0]\n"
218  "MRC p15, 0, R1,c3,c0\n" // write buffer config
219  "ADD R0, R0, #4\n"
220  "STR R1, [R0]\n"
221 
222  "MRC p15, 0, R1,c9,c1\n" // DTCM config
223  "ADD R0, R0, #4\n"
224  "STR R1, [R0]\n"
225 
226  "MRC p15, 0, R1,c9,c1,1\n" // ITCM config
227  "ADD R0, R0, #4\n"
228  "STR R1, [R0]\n"
229 
230  "BX LR\n"
231 
232  :::"r0","r1"
233  );
234 }
static const char* cache_tcm_size_str ( unsigned  val)
static

Definiert in Zeile 11 der Datei cpuinfo_v5.c.

11  {
12  if (val == 0)
13  return "0";
14  if (val < 3 || val > 11)
15  return "invalid";
16  return reg_sizes[val-3];
17 }
static const char* cache_words_line_str ( unsigned  val)
static

Definiert in Zeile 3 der Datei cpuinfo_v5.c.

3  {
4  switch(val) {
5  case 2: return "8";
6  default:
7  return "Unknown";
8  }
9 }
static const char* protreg_base_str ( unsigned  val)
static

Definiert in Zeile 29 der Datei cpuinfo_v5.c.

29  {
30  static char str[11];
31  sprintf(str,"0x%08X",val << 13);
32  return str;
33 }
static const char* protreg_size_str ( unsigned  val)
static

Definiert in Zeile 20 der Datei cpuinfo_v5.c.

20  {
21  if (val < 11 || val > 31)
22  return "invalid";
23  return reg_sizes[val - 11];
24 }
static const char* tcmcfg_size_str ( unsigned  val)
static

Definiert in Zeile 36 der Datei cpuinfo_v5.c.

36  {
37  if ( val < 3 || val > 23 )
38  return "invalid";
39  return reg_sizes[val - 3];
40 }

Variablen-Dokumentation

struct cpuinfo_bitfield_desc_s cpuinf_cachetype[]
Initialisierung:
= {
{2,"Icache words/line",cache_words_line_str},
{1,"Icache absent"},
{3,"Icache assoc"},
{4,"Icache size",cache_tcm_size_str},
{2,"Reserved0_2"},
{2,"Dcache words/line",cache_words_line_str},
{1,"Dcache absent"},
{3,"Dcache assoc"},
{4,"Dcache size",cache_tcm_size_str},
{2,"Reserved1_2"},
{1,"Harvard/unified"},
{4,"Cache type"},
{3,"Reserved2_3"},
{}
}

Definiert in Zeile 42 der Datei cpuinfo_v5.c.

struct cpuinfo_bitfield_desc_s cpuinf_control[]
Initialisierung:
= {
{1,"Protect enable"},
{1,"Reserved0_1"},
{1,"Dcache enable"},
{4,"Reserved1_4"},
{1,"Big endian"},
{4,"Reserved2_4"},
{1,"Icache enable"},
{1,"Alt vector"},
{1,"Cache RRR"},
{1,"Disble load TBIT"},
{1,"DTCM enable"},
{1,"DTCM mode"},
{1,"ITCM enable"},
{1,"ITCM mode"},
{12,"Reserved3_12"},
{}
}

Definiert in Zeile 72 der Datei cpuinfo_v5.c.

struct cpuinfo_bitfield_desc_s cpuinf_protreg[]
Initialisierung:
= {
{1,"Enable"},
{5,"Size",protreg_size_str},
{7,"Undef0_7"},
{19,"Base",protreg_base_str},
{}
}

Definiert in Zeile 103 der Datei cpuinfo_v5.c.

struct cpuinfo_bitfield_desc_s cpuinf_regbits[]
Initialisierung:
= {
{1,"Region 0"},
{1,"Region 1"},
{1,"Region 2"},
{1,"Region 3"},
{1,"Region 4"},
{1,"Region 5"},
{1,"Region 6"},
{1,"Region 7"},
{}
}

Definiert in Zeile 91 der Datei cpuinfo_v5.c.

struct cpuinfo_bitfield_desc_s cpuinf_regperms[]
Initialisierung:
= {
{4,"Region 0",regperm_str},
{4,"Region 1",regperm_str},
{4,"Region 2",regperm_str},
{4,"Region 3",regperm_str},
{4,"Region 4",regperm_str},
{4,"Region 5",regperm_str},
{4,"Region 6",regperm_str},
{4,"Region 7",regperm_str},
{}
}

Definiert in Zeile 111 der Datei cpuinfo_v5.c.

struct cpuinfo_bitfield_desc_s cpuinf_tcmcfg[]
Initialisierung:
= {
{1,"Reserved0_1"},
{5,"Size",tcmcfg_size_str},
{7,"Undef0_7"},
{19,"Base",protreg_base_str},
{}
}

Definiert in Zeile 123 der Datei cpuinfo_v5.c.

struct cpuinfo_bitfield_desc_s cpuinf_tcmtype[]
Initialisierung:
= {
{2,"Reserved0_2"},
{1,"ITCM absent"},
{3,"Reserved1_3"},
{4,"ITCM size",cache_tcm_size_str},
{4,"Reserved2_4"},
{1,"DTCM absent"},
{3,"Reserved3_2"},
{4,"DTCM size",cache_tcm_size_str},
{10,"Reserved4_10"},
{}
}

Definiert in Zeile 59 der Datei cpuinfo_v5.c.

struct cpuinfo_word_desc_s cpuinfo_desc[]
Initialisierung:
={
{"ID", cpuinf_id },
{"Cache type", cpuinf_cachetype },
{"TCM type", cpuinf_tcmtype },
{"Control", cpuinf_control },
{"Protection Region 0",cpuinf_protreg },
{"Protection Region 1",cpuinf_protreg },
{"Protection Region 2",cpuinf_protreg },
{"Protection Region 3",cpuinf_protreg },
{"Protection Region 4",cpuinf_protreg },
{"Protection Region 5",cpuinf_protreg },
{"Protection Region 6",cpuinf_protreg },
{"Protection Region 7",cpuinf_protreg },
{"Region data perms",cpuinf_regperms },
{"Region inst perms",cpuinf_regperms },
{"DCache cfg", cpuinf_regbits },
{"ICache cfg", cpuinf_regbits },
{"Write buffer", cpuinf_regbits },
{"DTCM cfg",cpuinf_tcmcfg },
{"ITCM cfg",cpuinf_tcmcfg },
{}
}

Definiert in Zeile 131 der Datei cpuinfo_v5.c.