cpuinfo_v5.c-Dateireferenz

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Funktionen
static const char *	cache_words_line_str (unsigned val)
static const char *	cache_tcm_size_str (unsigned val)
static const char *	protreg_size_str (unsigned val)
static const char *	protreg_base_str (unsigned val)
static const char *	tcmcfg_size_str (unsigned val)
void	__attribute__ ((naked, noinline))

Variablen
struct cpuinfo_bitfield_desc_s	cpuinf_cachetype []
struct cpuinfo_bitfield_desc_s	cpuinf_tcmtype []
struct cpuinfo_bitfield_desc_s	cpuinf_control []
struct cpuinfo_bitfield_desc_s	cpuinf_regbits []
struct cpuinfo_bitfield_desc_s	cpuinf_protreg []
struct cpuinfo_bitfield_desc_s	cpuinf_regperms []
struct cpuinfo_bitfield_desc_s	cpuinf_tcmcfg []
struct cpuinfo_word_desc_s	cpuinfo_desc []

Dokumentation der Funktionen

void __attribute__

(

(naked, noinline)

)

Definiert in Zeile 155 der Datei cpuinfo_v5.c.

                                                                                                 {
    asm (
        ".code 16\n"
        ".align 2\n"
        "BX      PC\n"                  // switch to ARM mode
        ".code 32\n"
        "MRC    p15, 0, R1,c0,c0\n" // ident
        "STR    R1, [R0]\n"
        "MRC    p15, 0, R1,c0,c0,1\n" // cache
        "ADD    R0, R0, #4\n"
        "STR    R1, [R0]\n"
        "MRC    p15, 0, R1,c0,c0,2\n" // TCM
        "ADD    R0, R0, #4\n"
        "STR    R1, [R0]\n"
        "MRC    p15, 0, R1,c1,c0\n" // control bits
        "ADD    R0, R0, #4\n"
        "STR    R1, [R0]\n"
        "MRC    p15, 0, R1,c6,c0\n" // protection region 0
        "ADD    R0, R0, #4\n"
        "STR    R1, [R0]\n"

        "MRC    p15, 0, R1,c6,c1\n" // protection region 1
        "ADD    R0, R0, #4\n"
        "STR    R1, [R0]\n"

        "MRC    p15, 0, R1,c6,c2\n" // protection region 2
        "ADD    R0, R0, #4\n"
        "STR    R1, [R0]\n"

        "MRC    p15, 0, R1,c6,c3\n" // protection region 3
        "ADD    R0, R0, #4\n"
        "STR    R1, [R0]\n"

        "MRC    p15, 0, R1,c6,c4\n" // protection region 4
        "ADD    R0, R0, #4\n"
        "STR    R1, [R0]\n"

        "MRC    p15, 0, R1,c6,c5\n" // protection region 5
        "ADD    R0, R0, #4\n"
        "STR    R1, [R0]\n"

        "MRC    p15, 0, R1,c6,c6\n" // protection region 6
        "ADD    R0, R0, #4\n"
        "STR    R1, [R0]\n"

        "MRC    p15, 0, R1,c6,c7\n" // protection region 7
        "ADD    R0, R0, #4\n"
        "STR    R1, [R0]\n"

        "MRC    p15, 0, R1,c5,c0,2\n" // data accesss perm
        "ADD    R0, R0, #4\n"
        "STR    R1, [R0]\n"

        "MRC    p15, 0, R1,c5,c0,3\n" // instruction accesss perm
        "ADD    R0, R0, #4\n"
        "STR    R1, [R0]\n"

        "MRC    p15, 0, R1,c2,c0\n" // data cache config
        "ADD    R0, R0, #4\n"
        "STR    R1, [R0]\n"
        "MRC    p15, 0, R1,c2,c0,1\n" // instruction cache config
        "ADD    R0, R0, #4\n"
        "STR    R1, [R0]\n"
        "MRC    p15, 0, R1,c3,c0\n" // write buffer config
        "ADD    R0, R0, #4\n"
        "STR    R1, [R0]\n"

        "MRC    p15, 0, R1,c9,c1\n" // DTCM config
        "ADD    R0, R0, #4\n"
        "STR    R1, [R0]\n"

        "MRC    p15, 0, R1,c9,c1,1\n" // ITCM config
        "ADD    R0, R0, #4\n"
        "STR    R1, [R0]\n"

        "BX     LR\n"

        :::"r0","r1"
    );
}

static const char* cache_tcm_size_str ( unsigned  val)

static

Definiert in Zeile 11 der Datei cpuinfo_v5.c.

                                                    {
    if (val == 0) 
        return "0";
    if (val < 3 || val > 11)
        return "invalid";
    return reg_sizes[val-3];
}

static const char* cache_words_line_str ( unsigned  val)

static

Definiert in Zeile 3 der Datei cpuinfo_v5.c.

                                                      {
    switch(val) {
        case 2: return "8";
        default:
            return "Unknown";
    }
}

static const char* protreg_base_str ( unsigned  val)

static

Definiert in Zeile 29 der Datei cpuinfo_v5.c.

                                                  {
    static char str[11];
    sprintf(str,"0x%08X",val << 13);
    return str;
}

static const char* protreg_size_str ( unsigned  val)

static

Definiert in Zeile 20 der Datei cpuinfo_v5.c.

                                                  {
    if (val < 11 || val > 31)
        return "invalid";
    return reg_sizes[val - 11];
}

static const char* tcmcfg_size_str ( unsigned  val)

static

Definiert in Zeile 36 der Datei cpuinfo_v5.c.

                                                 {
    if ( val < 3 || val > 23 ) 
        return "invalid";
    return reg_sizes[val - 3];
}

Variablen-Dokumentation

struct cpuinfo_bitfield_desc_s cpuinf_cachetype[]

Initialisierung:

= {
    {2,"Icache words/line",cache_words_line_str},
    {1,"Icache absent",0},
    {3,"Icache assoc",0},
    {4,"Icache size",cache_tcm_size_str},
    {2,"Reserved0_2",0},
    {2,"Dcache words/line",cache_words_line_str},
    {1,"Dcache absent",0},
    {3,"Dcache assoc",0},
    {4,"Dcache size",cache_tcm_size_str},
    {2,"Reserved1_2",0},
    {1,"Harvard/unified",0},
    {4,"Cache type",0},
    {3,"Reserved2_3",0},
    {0}
}

Definiert in Zeile 42 der Datei cpuinfo_v5.c.

struct cpuinfo_bitfield_desc_s cpuinf_control[]

Initialisierung:

= {
    {1,"Protect enable",0},
    {1,"Reserved0_1",0},
    {1,"Dcache enable",0},
    {4,"Reserved1_4",0},
    {1,"Big endian",0},
    {4,"Reserved2_4",0},
    {1,"Icache enable",0},
    {1,"Alt vector",0},
    {1,"Cache RRR",0},
    {1,"Disble load TBIT",0},
    {1,"DTCM enable",0},
    {1,"DTCM mode",0},
    {1,"ITCM enable",0},
    {1,"ITCM mode",0},
    {12,"Reserved3_12",0},
    {0}
}

Definiert in Zeile 72 der Datei cpuinfo_v5.c.

struct cpuinfo_bitfield_desc_s cpuinf_protreg[]

Initialisierung:

= {
    {1,"Enable",0},
    {5,"Size",protreg_size_str},
    {7,"Undef0_7",0},
    {19,"Base",protreg_base_str},
    {0}
}

Definiert in Zeile 103 der Datei cpuinfo_v5.c.

struct cpuinfo_bitfield_desc_s cpuinf_regbits[]

Initialisierung:

= {
    {1,"Region 0",0},
    {1,"Region 1",0},
    {1,"Region 2",0},
    {1,"Region 3",0},
    {1,"Region 4",0},
    {1,"Region 5",0},
    {1,"Region 6",0},
    {1,"Region 7",0},
    {0}
}

Definiert in Zeile 91 der Datei cpuinfo_v5.c.

struct cpuinfo_bitfield_desc_s cpuinf_regperms[]

Initialisierung:

= {
    {4,"Region 0",regperm_str},
    {4,"Region 1",regperm_str},
    {4,"Region 2",regperm_str},
    {4,"Region 3",regperm_str},
    {4,"Region 4",regperm_str},
    {4,"Region 5",regperm_str},
    {4,"Region 6",regperm_str},
    {4,"Region 7",regperm_str},
    {0}
}

Definiert in Zeile 111 der Datei cpuinfo_v5.c.

struct cpuinfo_bitfield_desc_s cpuinf_tcmcfg[]

Initialisierung:

= {
    {1,"Reserved0_1",0},
    {5,"Size",tcmcfg_size_str},
    {7,"Undef0_7",0},
    {19,"Base",protreg_base_str},
    {0}
}

Definiert in Zeile 123 der Datei cpuinfo_v5.c.

struct cpuinfo_bitfield_desc_s cpuinf_tcmtype[]

Initialisierung:

= {
    {2,"Reserved0_2",0},
    {1,"ITCM absent",0},
    {3,"Reserved1_3",0},
    {4,"ITCM size",cache_tcm_size_str},
    {4,"Reserved2_4",0},
    {1,"DTCM absent",0},
    {3,"Reserved3_2",0},
    {4,"DTCM size",cache_tcm_size_str},
    {10,"Reserved4_10",0},
    {0}
}

Definiert in Zeile 59 der Datei cpuinfo_v5.c.

struct cpuinfo_word_desc_s cpuinfo_desc[]

Initialisierung:

={
    {"ID", cpuinf_id },
    {"Cache type", cpuinf_cachetype },
    {"TCM type", cpuinf_tcmtype },
    {"Control", cpuinf_control },
    {"Protection Region 0",cpuinf_protreg },
    {"Protection Region 1",cpuinf_protreg },
    {"Protection Region 2",cpuinf_protreg },
    {"Protection Region 3",cpuinf_protreg },
    {"Protection Region 4",cpuinf_protreg },
    {"Protection Region 5",cpuinf_protreg },
    {"Protection Region 6",cpuinf_protreg },
    {"Protection Region 7",cpuinf_protreg },
    {"Region data perms",cpuinf_regperms },
    {"Region inst perms",cpuinf_regperms },
    {"DCache cfg", cpuinf_regbits },
    {"ICache cfg", cpuinf_regbits },
    {"Write buffer", cpuinf_regbits },
    {"DTCM cfg",cpuinf_tcmcfg },
    {"ITCM cfg",cpuinf_tcmcfg },
    {0}
}

Definiert in Zeile 131 der Datei cpuinfo_v5.c.