root/modules/cpuinfo_v5.c

DEFINITIONS

1. cache_words_line_str
2. cache_tcm_size_str
3. protreg_size_str
4. protreg_base_str
5. tcmcfg_size_str
6. cpuinfo_get_info

   1 // cpuinfo, ARMv5 specific parts
   3 static const char *cache_words_line_str(unsigned val) {
   4     switch(val) {
   5         case 2: return "8";
   6         default:
   7             return "Unknown";
   8     }
   9 }
  11 static const char *cache_tcm_size_str(unsigned val) {
  12     if (val == 0) 
  13         return "0";
  14     if (val < 3 || val > 11)
  15         return "invalid";
  16     return reg_sizes[val-3];
  17 }
  20 static const char *protreg_size_str(unsigned val) {
  21     if (val < 11 || val > 31)
  22         return "invalid";
  23     return reg_sizes[val - 11];
  24 }
  26 // "base" addresses actually overlap the rest of the register,
  27 // because the lower 13 are implicitly zero due to alignment constraints
  28 // here we return the actual address as a hex string
  29 static const char *protreg_base_str(unsigned val) {
  30         static char str[11];
sprintf(str,"0x%08X",val << 13);
  32         return str;
  33 }
  36 static const char *tcmcfg_size_str(unsigned val) {
  37     if ( val < 3 || val > 23 ) 
  38         return "invalid";
  39     return reg_sizes[val - 3];
  40 }
  42 const struct cpuinfo_bitfield_desc_s cpuinf_cachetype[] = {
  43     {2,"Icache words/line",cache_words_line_str},
  44     {1,"Icache absent",0},
  45     {3,"Icache assoc",0},
  46     {4,"Icache size",cache_tcm_size_str},
  47     {2,"Reserved0_2",0},
  48     {2,"Dcache words/line",cache_words_line_str},
  49     {1,"Dcache absent",0},
  50     {3,"Dcache assoc",0},
  51     {4,"Dcache size",cache_tcm_size_str},
  52     {2,"Reserved1_2",0},
  53     {1,"Harvard/unified",0},
  54     {4,"Cache type",0},
  55     {3,"Reserved2_3",0},
  56     {0}
  57 };
  59 const struct cpuinfo_bitfield_desc_s cpuinf_tcmtype[] = {
  60     {2,"Reserved0_2",0},
  61     {1,"ITCM absent",0},
  62     {3,"Reserved1_3",0},
  63     {4,"ITCM size",cache_tcm_size_str},
  64     {4,"Reserved2_4",0},
  65     {1,"DTCM absent",0},
  66     {3,"Reserved3_2",0},
  67     {4,"DTCM size",cache_tcm_size_str},
  68     {10,"Reserved4_10",0},
  69     {0}
  70 };
  72 const struct cpuinfo_bitfield_desc_s cpuinf_control[] = {
  73     {1,"Protect enable",0},
  74     {1,"Reserved0_1",0},
  75     {1,"Dcache enable",0},
  76     {4,"Reserved1_4",0},
  77     {1,"Big endian",0},
  78     {4,"Reserved2_4",0},
  79     {1,"Icache enable",0},
  80     {1,"Alt vector",0},
  81     {1,"Cache RRR",0},
  82     {1,"Disble load TBIT",0},
  83     {1,"DTCM enable",0},
  84     {1,"DTCM mode",0},
  85     {1,"ITCM enable",0},
  86     {1,"ITCM mode",0},
  87     {12,"Reserved3_12",0},
  88     {0}
  89 };
  91 const struct cpuinfo_bitfield_desc_s cpuinf_regbits[] = {
  92     {1,"Region 0",0},
  93     {1,"Region 1",0},
  94     {1,"Region 2",0},
  95     {1,"Region 3",0},
  96     {1,"Region 4",0},
  97     {1,"Region 5",0},
  98     {1,"Region 6",0},
  99     {1,"Region 7",0},
 100     {0}
 101 };
 103 const struct cpuinfo_bitfield_desc_s cpuinf_protreg[] = {
 104     {1,"Enable",0},
 105     {5,"Size",protreg_size_str},
 106     {7,"Undef0_7",0},
 107     {19,"Base",protreg_base_str},
 108     {0}
 109 };
 111 const struct cpuinfo_bitfield_desc_s cpuinf_regperms[] = {
 112     {4,"Region 0",regperm_str},
 113     {4,"Region 1",regperm_str},
 114     {4,"Region 2",regperm_str},
 115     {4,"Region 3",regperm_str},
 116     {4,"Region 4",regperm_str},
 117     {4,"Region 5",regperm_str},
 118     {4,"Region 6",regperm_str},
 119     {4,"Region 7",regperm_str},
 120     {0}
 121 };
 123 const struct cpuinfo_bitfield_desc_s cpuinf_tcmcfg[] = {
 124     {1,"Reserved0_1",0},
 125     {5,"Size",tcmcfg_size_str},
 126     {7,"Undef0_7",0},
 127     {19,"Base",protreg_base_str},
 128     {0}
 129 };
 131 const struct cpuinfo_word_desc_s cpuinfo_desc[]={
 132     {"ID", cpuinf_id },
 133     {"Cache type", cpuinf_cachetype },
 134     {"TCM type", cpuinf_tcmtype },
 135     {"Control", cpuinf_control },
 136     {"Protection Region 0",cpuinf_protreg },
 137     {"Protection Region 1",cpuinf_protreg },
 138     {"Protection Region 2",cpuinf_protreg },
 139     {"Protection Region 3",cpuinf_protreg },
 140     {"Protection Region 4",cpuinf_protreg },
 141     {"Protection Region 5",cpuinf_protreg },
 142     {"Protection Region 6",cpuinf_protreg },
 143     {"Protection Region 7",cpuinf_protreg },
 144     {"Region data perms",cpuinf_regperms },
 145     {"Region inst perms",cpuinf_regperms },
 146     {"DCache cfg", cpuinf_regbits },
 147     {"ICache cfg", cpuinf_regbits },
 148     {"Write buffer", cpuinf_regbits },
 149     {"DTCM cfg",cpuinf_tcmcfg },
 150     {"ITCM cfg",cpuinf_tcmcfg },
 151     {0}
 152 };
 155 void __attribute__((naked,noinline)) cpuinfo_get_info(__attribute__ ((unused))unsigned *results) {
 156     asm (
 157         ".code 16\n"
 158         ".align 2\n"
 159         "BX      PC\n"                  // switch to ARM mode
 160         ".code 32\n"
 161         "MRC    p15, 0, R1,c0,c0\n" // ident
 162         "STR    R1, [R0]\n"
 163         "MRC    p15, 0, R1,c0,c0,1\n" // cache
 164         "ADD    R0, R0, #4\n"
 165         "STR    R1, [R0]\n"
 166         "MRC    p15, 0, R1,c0,c0,2\n" // TCM
 167         "ADD    R0, R0, #4\n"
 168         "STR    R1, [R0]\n"
 169         "MRC    p15, 0, R1,c1,c0\n" // control bits
 170         "ADD    R0, R0, #4\n"
 171         "STR    R1, [R0]\n"
 172         "MRC    p15, 0, R1,c6,c0\n" // protection region 0
 173         "ADD    R0, R0, #4\n"
 174         "STR    R1, [R0]\n"
 176         "MRC    p15, 0, R1,c6,c1\n" // protection region 1
 177         "ADD    R0, R0, #4\n"
 178         "STR    R1, [R0]\n"
 180         "MRC    p15, 0, R1,c6,c2\n" // protection region 2
 181         "ADD    R0, R0, #4\n"
 182         "STR    R1, [R0]\n"
 184         "MRC    p15, 0, R1,c6,c3\n" // protection region 3
 185         "ADD    R0, R0, #4\n"
 186         "STR    R1, [R0]\n"
 188         "MRC    p15, 0, R1,c6,c4\n" // protection region 4
 189         "ADD    R0, R0, #4\n"
 190         "STR    R1, [R0]\n"
 192         "MRC    p15, 0, R1,c6,c5\n" // protection region 5
 193         "ADD    R0, R0, #4\n"
 194         "STR    R1, [R0]\n"
 196         "MRC    p15, 0, R1,c6,c6\n" // protection region 6
 197         "ADD    R0, R0, #4\n"
 198         "STR    R1, [R0]\n"
 200         "MRC    p15, 0, R1,c6,c7\n" // protection region 7
 201         "ADD    R0, R0, #4\n"
 202         "STR    R1, [R0]\n"
 204         "MRC    p15, 0, R1,c5,c0,2\n" // data accesss perm
 205         "ADD    R0, R0, #4\n"
 206         "STR    R1, [R0]\n"
 208         "MRC    p15, 0, R1,c5,c0,3\n" // instruction accesss perm
 209         "ADD    R0, R0, #4\n"
 210         "STR    R1, [R0]\n"
 212         "MRC    p15, 0, R1,c2,c0\n" // data cache config
 213         "ADD    R0, R0, #4\n"
 214         "STR    R1, [R0]\n"
 215         "MRC    p15, 0, R1,c2,c0,1\n" // instruction cache config
 216         "ADD    R0, R0, #4\n"
 217         "STR    R1, [R0]\n"
 218         "MRC    p15, 0, R1,c3,c0\n" // write buffer config
 219         "ADD    R0, R0, #4\n"
 220         "STR    R1, [R0]\n"
 222         "MRC    p15, 0, R1,c9,c1\n" // DTCM config
 223         "ADD    R0, R0, #4\n"
 224         "STR    R1, [R0]\n"
 226         "MRC    p15, 0, R1,c9,c1,1\n" // ITCM config
 227         "ADD    R0, R0, #4\n"
 228         "STR    R1, [R0]\n"
 230         "BX     LR\n"
 232         :::"r0","r1"
 233     );
 234 }