root/loader/m3/main.c

DEFINITIONS

1. my_restart
2. clean_data_cache_line_my

   1 #include "../generic/check_compat.c"
   3 extern long *blob_chdk_core;
   4 extern long blob_chdk_core_size;
   6 void __attribute__((noreturn)) my_restart()
   7 {
check_compat();
  10     // light up green LED
  11     *(int*)0xd20b0994 = 0x4d0002;
  12     // LED done
  13     long *dst = (long*)MEMISOSTART;
  14     const long *src = blob_chdk_core;
  15     long length = (blob_chdk_core_size + 3) >> 2;
core_copy(src, dst, length);
  19     asm volatile (
  20     "mov     r1, %1\n"
  21     "mov     r0, %0\n"
  22     // caching related routine called at fw startup
  23     "blx     clean_data_cache_line_my\n" // function copied since address varies between 101a (0xc1300b3) and 120f(0xfc13019b)
  24     "mov     r0, %0\n"
  25     "add     r0, r0, #1\n"
  26     "bx      r0\n"
  27     : : "r"(MEMISOSTART), "r"(((blob_chdk_core_size+3)>>2)<<2) : "memory","r0","r1","r2","r3","r4"
  28     );
  29     while(1);
  30 }
  32 void __attribute__((naked,noinline)) clean_data_cache_line_my() {
  33     asm volatile (
  34 " loc_fc13019a:\n"
  35 "     cmp.w   r1, #0x4000\n"
  36 "     bcs.n   loc_fc1301bc\n"
  37 "     dsb sy\n"
  38 "     add r1, r0\n"
  39 "     bic.w   r0, r0, #0x1f\n"
  40 " loc_fc1301aa:\n"
  41 "     mcr 15, 0, r0, cr7, cr10, 1\n"
  42 "     add.w   r0, r0, #0x20\n"
  43 "     cmp r0, r1\n"
  44 "     bcc.n   loc_fc1301aa\n"
  45 "     dsb sy\n"
  46 "     bx  lr\n"
  47 " loc_fc1301bc:\n"
  48 "     dsb sy\n"
  49 "     mov.w   r1, #0\n"
  50 " loc_fc1301c4:\n"
  51 "     mov.w   r0, #0\n"
  52 " loc_fc1301c8:\n"
  53 "     orr.w   r2, r1, r0\n"
  54 "     mcr 15, 0, r2, cr7, cr10, 2\n"
  55 "     add.w   r0, r0, #0x20\n"
  56 "     cmp.w   r0, #0x1000\n"
  57 "     bne.n   loc_fc1301c8\n"
  58 "     add.w   r1, r1, #0x40000000\n"
  59 "     cmp r1, #0\n"
  60 "     bne.n   loc_fc1301c4\n"
  61 "     dsb sy\n"
  62 "     bx  lr\n"
  63 ".ltorg\n"
  64     );
  65 }