1 #include "lolevel.h"
2 #include "platform.h"
3 #include "core.h"
4
5 static long *nrflag = (long*)0xED44;
6
7 #include "../../../generic/capt_seq.c"
8
9 void __attribute__((naked,noinline)) sub_FFB0D8E4_my(long p)
10 {
11 (void)p;
12 asm volatile (
13 " STMFD SP!, {R4,LR}\n"
14 " BL sub_FFB0D420\n"
15 " LDR R3, =0xAAB80\n"
16 " LDR R2, [R3,#0x24]\n"
17 " CMP R2, #0\n"
18 " MOV R4, R0\n"
19 " MOV R0, #0xC\n"
20 " BEQ loc_FFB0D92C\n"
21 " BL sub_FFB17EE8\n"
22 " TST R0, #1\n"
23 " BEQ loc_FFB0D92C\n"
24 " LDR R3, [R4,#8]\n"
25 " LDR R2, =0xED30\n"
26 " ORR R3, R3, #0x40000000\n"
27 " MOV R1, #1\n"
28 " STR R1, [R2]\n"
29 " STR R3, [R4,#8]\n"
30 " LDMFD SP!, {R4,PC}\n"
31 "loc_FFB0D92C:\n"
32 " BL sub_FF826284\n"
33 " BL sub_FF81BE94\n"
34 " STR R0, [R4,#0x14]\n"
35 " MOV R0, R4\n"
36 "BL sub_FFB10B64_my\n" //---> escape to My!
37 "BL capt_seq_hook_raw_here\n" // + <----- RAW hook
38 " TST R0, #1\n"
39 " LDRNE R3, =0xED30\n"
40 " MOVNE R2, #1\n"
41 " STRNE R2, [R3]\n"
42 " LDMFD SP!, {R4,PC}\n"
43 );
44 }
45
46 void __attribute__((naked,noinline)) sub_FFB10B64_my(long p)
47 {
48 (void)p;
49 asm volatile (
50 " STMFD SP!, {R4,LR}\n"
51 " MOV R4, R0\n"
52 " SUB SP, SP, #0xC\n"
53 " BL sub_FFB115D4\n"
54
55 //" MOVL R1, 0xFFFFFFFF\n" // asm doesn't like this. Thus:
56 "MVN R1, #0\n"
57
58 " BL sub_FFB21E2C\n" //ClearEventFlag
59 " MOV R0, #0x8A\n"
60 " ADD R1, SP, #4\n"
61 " MOV R2, #4\n"
62 " BL sub_FF81BC98\n"
63 " TST R0, #1\n"
64 " BEQ loc_FFB10BA4\n"
65
66 " MOV R1, #0x1D0\n"
67 // means: " MOV R1, #0x1D,28\n"
68
69 " LDR R0, =0xFFB109E8\n" //"SsCaptureSeq.c"
70 " ADD R1, R1, #2\n"
71 " BL sub_FFB2F4F0\n" //DebugAssert
72 "loc_FFB10BA4:\n"
73 " LDR R3, =0xAAB80\n"
74 " LDR R2, =0xAAC40\n"
75 " LDR R0, [R3,#0x7C]\n"
76 " LDRSH R1, [R2,#0xE]\n"
77 " BL sub_FFA4226C\n"
78 " MOV R0, R4\n"
79 " BL sub_FFB1096C\n"
80 "BL wait_until_remote_button_is_released\n"
81 "BL capt_seq_hook_set_nr\n" // + <- ADDED !!!!!
82 " LDR R3, =0xED48\n"
83 " LDR R0, [R3]\n"
84 "B sub_FFB10BC8\n" // ---> jump to the original code in ROM, see below
85 //FFB10BC8 BL sub_FFA42780
86 );
87 }
88
89 // orig. is sub_FFB0D80C
90 void __attribute__((naked,noinline)) sub_FFB0D80C_my(long p)
91 {
92 (void)p;
93 asm volatile (
94
95 " STMFD SP!, {R4,R5,LR}\n"
96 " LDR R5, =0xAAB80\n"
97 " LDR R4, [R0,#0xC]\n"
98 " LDR R2, [R5,#0x24]\n"
99 " LDR R3, [R4,#8]\n"
100 " CMP R2, #0\n"
101 " ORR R3, R3, #1\n"
102 " STR R3, [R4,#8]\n"
103 " BNE loc_FFB0D838\n"
104 " MOV R0, #2\n"
105 " BL sub_FFAF1CA4\n"
106 "loc_FFB0D838:\n"
107 " BL sub_FFB0E394\n" //Set_CMD25Write_62
108 " LDR R3, [R5,#0x24]\n"
109 " CMP R3, #0\n"
110 " BNE loc_FFB0D8A4\n"
111 " MOV R0, R4\n"
112 " BL sub_FFB0F59C\n"
113 " TST R0, #1\n"
114 " BEQ loc_FFB0D868\n"
115 " MOV R2, R4\n"
116 " MOV R1, #1\n"
117 " LDMFD SP!, {R4,R5,LR}\n"
118 " B sub_FFB0BF7C\n"
119 "loc_FFB0D868:\n"
120 " BL sub_FF826284\n"
121 " BL sub_FF81BE94\n"
122 " LDRH R2, [R5]\n"
123 //" MOVL R3, 0x420F\n" // asm doesn't understand this. Thus:
124 "MOV R3, #0x4200\n"
125 // means: "MOV R3, #0x42,24\n"
126 "ADD R3, R3, #0xF\n"
127
128 " CMP R2, R3\n"
129 " STR R0, [R4,#0x14]\n"
130 " BNE loc_FFB0D88C\n"
131 " BL sub_FFAF185C\n"
132 "loc_FFB0D88C:\n"
133 " MOV R0, R4\n"
134 " BL sub_FFB10A4C\n"
135 " BL sub_FFB11440\n"
136 " MOV R0, R4\n"
137 //" BL sub_FFB10B64\n"
138 "BL sub_FFB10B64_my\n" //---------> ESCAPE to My !!!!!
139 "BL capt_seq_hook_raw_here\n" // + <- ADDED !!!!!
140 " B loc_FFB0D8B8\n"
141 "loc_FFB0D8A4:\n"
142 " LDR R3, =0xED30\n"
143 " LDR R2, [R3]\n"
144 " CMP R2, #0\n"
145 " MOVNE R0, #0x1D\n"
146 " MOVEQ R0, #0\n"
147 "loc_FFB0D8B8:\n"
148 " MOV R1, #1\n"
149 " MOV R2, R4\n"
150 " BL sub_FFB0BF7C\n"
151 " BL sub_FFB10EE0\n"
152 " CMP R0, #0\n"
153 " LDRNE R3, [R4,#8]\n"
154 " ORRNE R3, R3, #0x2000\n"
155 " STRNE R3, [R4,#8]\n"
156 " LDMFD SP!, {R4,R5,PC}\n"
157 );
158 }
159
160 // orig. at FFB0DD10
161 void __attribute__((naked,noinline)) capt_seq_task()
162 {
163 asm volatile (
164 " STMFD SP!, {R4,LR}\n"
165 " SUB SP, SP, #4\n"
166 " MOV R4, SP\n"
167 " B loc_FFB0DEB4\n"
168 "loc_FFB0DD20:\n"
169 " LDR R2, [SP]\n"
170 " LDR R3, [R2]\n"
171 " MOV R0, R2\n"
172 " CMP R3, #0x17\n"
173 " LDRLS PC, [PC,R3,LSL#2]\n"
174 " B loc_FFB0DE88\n"
175 " .long loc_FFB0DD98\n"
176 " .long loc_FFB0DDB8\n"
177 " .long loc_FFB0DDCC\n"
178 " .long loc_FFB0DDE0\n"
179 " .long loc_FFB0DDD8\n"
180 " .long loc_FFB0DDE8\n"
181 " .long loc_FFB0DDF0\n"
182 " .long loc_FFB0DDFC\n"
183 " .long loc_FFB0DE04\n"
184 " .long loc_FFB0DE10\n"
185 " .long loc_FFB0DE18\n"
186 " .long loc_FFB0DE20\n"
187 " .long loc_FFB0DE28\n"
188 " .long loc_FFB0DE30\n"
189 " .long loc_FFB0DE38\n"
190 " .long loc_FFB0DE40\n"
191 " .long loc_FFB0DE48\n"
192 " .long loc_FFB0DE54\n"
193 " .long loc_FFB0DE5C\n"
194 " .long loc_FFB0DE64\n"
195 " .long loc_FFB0DE6C\n"
196 " .long loc_FFB0DE78\n"
197 " .long loc_FFB0DE80\n"
198 " .long loc_FFB0DE9C\n"
199 "loc_FFB0DD98:\n"
200 " BL sub_FFB0E3BC\n"
201 // only do quick press hack if overrides are active
202 " BL captseq_hack_override_active\n" // returns 1 if tv or sv override in effect
203 " STR R0,[SP,#-4]!\n" // push return value
204 "BL shooting_expo_param_override\n" // + <- ADDED !!!!!
205 " BL sub_FFB0BA04\n"
206 " LDR R3, =0xAAB80\n"
207 " LDR R0,[SP],#4\n" // pop override hack
208 " CMP R0, #1\n" // +
209 " MOVEQ R0, #0\n" // +
210 " STREQ R0, [R3,#0x24]\n" // fixes overrides behavior at short shutter press
211 " LDRNE R0, [R3,#0x24]\n" // modified NE
212 " CMPNE R0, #0\n" // modified NE
213 " BEQ loc_FFB0DE98\n"
214 " BL sub_FFB0D8E4_my\n" //<---- extra RAW hook inside
215 " B loc_FFB0DE98\n"
216 "loc_FFB0DDB8:\n"
217 //" BL sub_FFB0D80C\n"
218 " BL sub_FFB0D80C_my\n" //---------> ESCAPE to My !!!!!
219 "loc_FFB0DDBC:\n"
220 " LDR R2, =0xAAB80\n"
221 " MOV R3, #0\n"
222 " STR R3, [R2,#0x24]\n"
223 " B loc_FFB0DE98\n"
224 "loc_FFB0DDCC:\n"
225 " MOV R0, #1\n"
226 " BL sub_FFB0E5E8\n"
227 " B loc_FFB0DE98\n"
228 "loc_FFB0DDD8:\n"
229 " BL sub_FFB0DFA0\n"
230 " B loc_FFB0DDBC\n"
231 "loc_FFB0DDE0:\n"
232 " BL sub_FFB0E374\n" //BackLightDrv_LcdBackLightOff_16
233 " B loc_FFB0DDBC\n"
234 "loc_FFB0DDE8:\n"
235 " BL sub_FFB0E384\n"
236 " B loc_FFB0DE98\n"
237 "loc_FFB0DDF0:\n"
238 " BL sub_FFB0E4D8\n"
239 " BL sub_FFB0BA04\n"
240 " B loc_FFB0DE98\n"
241 "loc_FFB0DDFC:\n"
242 " BL sub_FFB0D9BC\n"
243 " B loc_FFB0DE98\n"
244 "loc_FFB0DE04:\n"
245 " BL sub_FFB0E54C\n"
246 " BL sub_FFB0BA04\n"
247 " B loc_FFB0DE98\n"
248 "loc_FFB0DE10:\n"
249 " BL sub_FFB0E374\n" //BackLightDrv_LcdBackLightOff_16
250 " B loc_FFB0DE98\n"
251 "loc_FFB0DE18:\n"
252 " BL sub_FFB0FCD0\n"
253 " B loc_FFB0DE98\n"
254 "loc_FFB0DE20:\n"
255 " BL sub_FFB0FEA4\n"
256 " B loc_FFB0DE98\n"
257 "loc_FFB0DE28:\n"
258 " BL sub_FFB0FF38\n"
259 " B loc_FFB0DE98\n"
260 "loc_FFB0DE30:\n"
261 " BL sub_FFB10034\n"
262 " B loc_FFB0DE98\n"
263 "loc_FFB0DE38:\n"
264 " BL sub_FFB102BC\n"
265 " B loc_FFB0DE98\n"
266 "loc_FFB0DE40:\n"
267 " BL sub_FFB1030C\n"
268 " B loc_FFB0DE98\n"
269 "loc_FFB0DE48:\n"
270 " MOV R0, #0\n"
271 " BL sub_FFB10360\n"
272 " B loc_FFB0DE98\n"
273 "loc_FFB0DE54:\n"
274 " BL sub_FFB10534\n"
275 " B loc_FFB0DE98\n"
276 "loc_FFB0DE5C:\n"
277 " BL sub_FFB105D0\n"
278 " B loc_FFB0DE98\n"
279 "loc_FFB0DE64:\n"
280 " BL sub_FFB1069C\n"
281 " B loc_FFB0DE98\n"
282 "loc_FFB0DE6C:\n"
283 " BL sub_FFB0E73C\n"
284 " BL sub_FFB0D730\n"
285 " B loc_FFB0DE98\n"
286 "loc_FFB0DE78:\n"
287 " BL sub_FFB10174\n"
288 " B loc_FFB0DE98\n"
289 "loc_FFB0DE80:\n"
290 " BL sub_FFB101D0\n"
291 " B loc_FFB0DE98\n"
292 "loc_FFB0DE88:\n"
293 " MOV R1, #0x4F0\n"
294 " LDR R0, =0xFFB0D58C\n" //=aSsshoottask_c
295 " ADD R1, R1, #1\n"
296 " BL sub_FFB2F4F0\n" //DebugAssert
297 "loc_FFB0DE98:\n"
298 " LDR R2, [SP]\n"
299 "loc_FFB0DE9C:\n"
300 " LDR R3, =0x84428\n"
301 " LDR R1, [R2,#4]\n"
302 " LDR R0, [R3]\n"
303 " BL sub_FFB21C90\n" //SetEventFlag
304 " LDR R0, [SP]\n"
305 " BL sub_FFB0D60C\n"
306 "loc_FFB0DEB4:\n"
307 " LDR R3, =0x8442C\n"
308 " MOV R1, R4\n"
309 " LDR R0, [R3]\n"
310 " MOV R2, #0\n"
311 " BL sub_FFB223A8\n" //ReceiveMessageQueue
312 " TST R0, #1\n"
313 " BEQ loc_FFB0DD20\n"
314 " MOV R1, #0x410\n"
315 " LDR R0, =0xFFB0D58C\n" //=aSsshoottask_c
316 " ADD R1, R1, #5\n"
317 " BL sub_FFB2F4F0\n" //DebugAssert
318 " BL sub_FFB2396C\n"
319 " ADD SP, SP, #4\n"
320 " LDMFD SP!, {R4,PC}\n"
321 );
322 }
323
324
325
326
327
328
329
330 /*
331 ROM:FF976A78 var_38 = -0x38
332 ROM:FF976A78 var_34 = -0x34
333 ROM:FF976A78 var_30 = -0x30
334 ROM:FF976A78 var_24 = -0x24
335 ROM:FF976A78 var_20 = -0x20
336 ROM:FF976A78 var_1E = -0x1E
337 ROM:FF976A78 var_1C = -0x1C
338 */
339 //void __attribute__((naked,noinline)) _task_ExpDrvTask() {
340 void __attribute__((naked,noinline)) exp_drv_task() {
341 asm volatile(
342 "STMFD SP!, {R4-R8,LR}\n" // @ Store Block to Memory
343 "SUB SP, SP, #0x20\n" // @ Rd = Op1 - Op2
344 "ADD R7, SP, #0x4\n" // @ Rd = Op1 + Op2
345 "B loc_FF976F88\n" // @ Branch
346
347
348 "loc_FF976A88:\n" // @ CODE XREF: task_ExpDrvTask+530
349 "CMP R2, #0x22\n" // @ '"' @ Set cond. codes on Op1 - Op2
350 "BNE loc_FF976AA0\n" //@ Branch
351
352 "LDR R0, [R12,#0x8C]\n" //@ Load from Memory
353 "MOV LR, PC\n" //@ Rd = Op2
354 "LDR PC, [R12,#0x88]\n" //@ Indirect Jump
355 "B loc_FF976B04\n" //@ Branch
356
357
358
359 "loc_FF976AA0:\n" //@ CODE XREF: task_ExpDrvTask+14
360 "CMP R2, #0x1D\n" //@ Set cond. codes on Op1 - Op2
361 "BNE loc_FF976AB4\n" //@ Branch
362
363 "MOV R0, R12\n" //@ Rd = Op2
364 "BL sub_FF976948\n" //@ Branch with Link
365
366 "B loc_FF976AF4\n" //@ Branch
367
368
369
370 "loc_FF976AB4:\n" //@ CODE XREF: task_ExpDrvTask+2C
371 "CMP R2, #0x1E\n" //@ Set cond. codes on Op1 - Op2
372 "BNE loc_FF976AC8\n" //@ Branch
373
374 "MOV R0, R12\n" //@ Rd = Op2
375 "BL sub_FF9769A4\n" //@ Branch with Link
376
377 "B loc_FF976AF4\n" //@ Branch
378
379
380
381 "loc_FF976AC8:\n" //@ CODE XREF: task_ExpDrvTask+40
382 "SUB R3, R2, #0x1F\n" //@ Rd = Op1 - Op2
383 "CMP R3, #1\n" //@ Set cond. codes on Op1 - Op2
384 "BHI loc_FF976AE0\n" //@ Branch
385
386 "MOV R0, R12\n" //@ Rd = Op2
387 "BL sub_FF976A00\n" //@ Branch with Link
388
389 "B loc_FF976AF4\n" //@ Branch
390
391
392
393 "loc_FF976AE0:\n" //@ CODE XREF: task_ExpDrvTask+58
394 "CMP R2, #0x21\n" // @ '!' Set cond. codes on Op1 - Op2
395 "BNE loc_FF976B10\n" //@ Branch
396
397 "BL sub_FF93C0BC\n" //@ Branch with Link
398
399 "BL sub_FF93F1F4\n" //@ Branch with Link
400
401 "BL sub_FF93E42C\n" //@ Branch with Link
402
403
404 "loc_FF976AF4:\n" //@ CODE XREF: task_ExpDrvTask+38
405 "LDR R3, [SP,#4]\n" //@ Load from Memory
406 "LDR R0, [R3,#0x8C]\n" //@ Load from Memory
407 "MOV LR, PC\n" //@ Rd = Op2
408 "LDR PC, [R3,#0x88]\n" //@ Indirect Jump
409
410 "loc_FF976B04:\n" //@ CODE XREF: task_ExpDrvTask+24
411 "LDR R0, [SP,#0x4]\n" //@ Load from Memory
412 "BL sub_FF9722A8\n" //@ Branch with Link
413
414 "B loc_FF976F88\n" //@ Branch
415
416
417 "loc_FF976B10:\n" //@ CODE XREF: task_ExpDrvTask+6C
418 "CMP R2, #0xD\n" //@ Set cond. codes on Op1 - Op2
419 "MOV R8, #1\n" //@ Rd = Op2
420 "BNE loc_FF976B80\n" //@ Branch
421
422 "LDR R1, [R12,#0x7C]\n" //@ Load from Memory
423 "ADD R1, R1, R1,LSL#1\n" //@ Rd = Op1 + Op2
424 "ADD R1, R12, R1,LSL#2\n" //@ Rd = Op1 + Op2
425 "ADD R6, SP, #0x14\n" //@ Rd = Op1 + Op2
426 "SUB R1, R1, #8\n" //@ Rd = Op1 - Op2
427 "MOV R2, #0xC\n" //@ Rd = Op2
428 "MOV R0, R6\n" //@ Rd = Op2
429 "BL _memcpy\n" //@ Branch with Link
430
431 "LDR R0, [SP,#4]\n" //@ Load from Memory
432 "BL sub_FF974F0C\n" //@ Branch with Link
433
434 "LDR R3, [SP,#04]\n" //@ Load from Memory
435 "LDR R1, [R3,#0x7C]\n" //@ Load from Memory
436 "LDR R2, [R3,#0x8C]\n" //@ Load from Memory
437 "ADD R0, R3, #4\n" //@ Rd = Op1 + Op2
438 "MOV LR, PC\n" //@ Rd = Op2
439 "LDR PC, [R3,#0x88]\n" //@ Indirect Jump
440 "LDR R0, [SP,#4]\n" //@ Load from Memory
441 "BL sub_FF9751D8\n" //@ Branch with Link
442
443 "LDR R3, [SP,#04]\n" //@ Load from Memory
444 "ADD R0, R3, #4\n" //@ Rd = Op1 + Op2
445 "LDR R1, [R3,#0x7C]\n" //@ Load from Memory
446 "LDR R2, [R3,#0x94]\n" //@ Load from Memory
447 "MOV LR, PC\n" //@ Rd = Op2
448 "LDR PC, [R3,#0x90]\n" //@ Indirect Jump
449 "B loc_FF976ED0\n" //@ Branch
450
451
452
453 "loc_FF976B80:\n" //@ CODE XREF: task_ExpDrvTask+A0
454 "SUB R3, R2, #0xE\n" //@ Rd = Op1 - Op2
455 "CMP R3, #1\n" //@ Set cond. codes on Op1 - Op2
456 "BHI loc_FF976C3C\n" //@ Branch
457
458 "ADD R6, SP, #0x14\n" //@ Rd = Op1 + Op2
459 "ADD R5, SP, #0x8\n" //@ Rd = Op1 + Op2
460 "MOV R0, R12\n" //@ Rd = Op2
461 "MOV R1, R6\n" //@ Rd = Op2
462 "MOV R2, R5\n" //@ Rd = Op2
463 "BL sub_FF9752C8\n" //@ Branch with Link
464
465 "MOV R4, R0\n" //@ Rd = Op2
466 "CMP R4, #5\n" //@ Set cond. codes on Op1 - Op2
467 "CMPNE R4, #1\n" //@ Set cond. codes on Op1 - Op2
468 "BNE loc_FF976BD4\n" //@ Branch
469
470 "LDR R12, [SP,#0x4]\n" //@ Load from Memory
471 "MOV R0, R5\n" //@ Rd = Op2
472 "LDR R1, [R12,#0x7C]\n" //@ Load from Memory
473 "MOV R2, R4\n" //@ Rd = Op2
474 "LDR R3, [R12,#0x8C]\n" //@ Load from Memory
475 "MOV LR, PC\n" //@ Rd = Op2
476 "LDR PC, [R12,#0x88]\n" //@ Indirect Jump
477 "B loc_FF976C0C\n" //@ Branch
478
479
480
481 "loc_FF976BD4:\n" //@ CODE XREF: task_ExpDrvTask+138
482 "CMP R4, #6\n" //@ Set cond. codes on Op1 - Op2
483 "CMPNE R4, #2\n" //@ Set cond. codes on Op1 - Op2
484 "BNE loc_FF976C1C\n" //@ Branch
485
486 "LDR R12, [SP,#0x4]\n" //@ Load from Memory
487 "MOV R0, R5\n" //@ Rd = Op2
488 "MOV R1, R8\n" //@ Rd = Op2
489 "MOV R2, R4\n" //@ Rd = Op2
490 "LDR R3, [R12,#0x8C]\n" //@ Load from Memory
491 "MOV LR, PC\n" //@ Rd = Op2
492 "LDR PC, [R12,#0x88]\n" //@ Indirect Jump
493 "MOV R1, R6\n" //@ Rd = Op2
494 "LDR R0, [SP,#0x4]\n" //@ Load from Memory
495 "MOV R2, R5\n" //@ Rd = Op2
496 "BL sub_FF976578\n" //@ Branch with Link
497
498
499 "loc_FF976C0C:\n" //@ CODE XREF: task_ExpDrvTask+158
500 "MOV R1, R4\n" //@ Rd = Op2
501 "LDR R0, [SP,#04]\n" //@ Load from Memory
502 "BL sub_FF9768DC\n" //@ Branch with Link
503
504 "B loc_FF976ED0\n" //@ Branch
505
506
507 "loc_FF976C1C:\n" //@ CODE XREF: task_ExpDrvTask+164
508 "LDR R12, [SP,#0x4]\n" //@ Load from Memory
509 "MOV R2, R4\n" //@ Rd = Op2
510 "ADD R0, R12, #4\n" //@ Rd = Op1 + Op2
511 "LDR R1, [R12,#0x7C]\n" //@ Load from Memory
512 "LDR R3, [R12,#0x8C]\n" //@ Load from Memory
513 "MOV LR, PC\n" //@ Rd = Op2
514 "LDR PC, [R12,#0x88]\n" //@ Indirect Jump
515 "B loc_FF976ED0\n" //@ Branch
516
517
518
519 "loc_FF976C3C:\n" //@ CODE XREF: task_ExpDrvTask+110
520 "SUB R3, R2, #0x19\n" //@ Rd = Op1 - Op2
521 "CMP R3, #1\n" //@ Set cond. codes on Op1 - Op2
522 "BHI loc_FF976C94\n" //@ Branch
523
524 "LDR R1, [R12,#0x7C]\n" //@ Load from Memory
525 "ADD R1, R1, R1,LSL#1\n" //@ Rd = Op1 + Op2
526 "ADD R1, R12, R1,LSL#2\n" //@ Rd = Op1 + Op2
527 "ADD R6, SP, #0x14\n" //@ Rd = Op1 + Op2
528 "SUB R1, R1, #8\n" //@ Rd = Op1 - Op2
529 "MOV R2, #0xC\n" //@ Rd = Op2
530 "MOV R0, R6\n" //@ Rd = Op2
531 "BL _memcpy\n" //@ Branch with Link
532
533 "LDR R0, [SP,#0x4]\n" //@ Load from Memory
534 "BL sub_FF97430C\n" //@ Branch with Link
535
536 "LDR R3, [SP,#0x4]\n" //@ Load from Memory
537 "ADD R0, R3, #4\n" //@ Rd = Op1 + Op2
538 "LDR R1, [R3,#0x7C]\n" //@ Load from Memory
539 "LDR R2, [R3,#0x8C]\n" //@ Load from Memory
540 "MOV LR, PC\n" //@ Rd = Op2
541 "LDR PC, [R3,#0x88]\n" //@ Indirect Jump
542 "LDR R0, [SP,#0x4]\n" //@ Load from Memory
543 "BL sub_FF97462C\n" //@ Branch with Link
544
545 "B loc_FF976ED0\n" //@ Branch
546
547
548
549 "loc_FF976C94:\n" //@ CODE XREF: task_ExpDrvTask+1CC
550 "ADD R6, SP, #0x14\n" //@ Rd = Op1 + Op2
551 "ADD R1, R12, #4\n" //@ Rd = Op1 + Op2
552 "MOV R2, #0xC\n" //@ Rd = Op2
553 "MOV R0, R6\n" //@ Rd = Op2
554 "BL _memcpy\n" //@ Branch with Link
555
556 "LDR R12, [SP,#0x4]\n" //@ Load from Memory
557 "LDR R3, [R12]\n" //@ Load from Memory
558 "MOV R2, R12\n" //@ Rd = Op2
559 "CMP R3, #0x1C\n" //@ Set cond. codes on Op1 - Op2
560 "LDRLS PC, [PC,R3,LSL#2]\n" //@ Indirect Jump
561
562 "B loc_FF976EBC\n" //@ Branch
563
564
565 ".long loc_FF976D34\n"
566 ".long loc_FF976D40\n"
567 ".long loc_FF976D4C\n"
568 ".long loc_FF976D4C\n"
569 ".long loc_FF976D34\n"
570 ".long loc_FF976D40\n"
571 ".long loc_FF976D4C\n"
572 ".long loc_FF976D4C\n"
573 ".long loc_FF976D70\n"
574 ".long loc_FF976D70\n"
575 ".long loc_FF976E90\n"
576 ".long loc_FF976E9C\n"
577 ".long loc_FF976EAC\n"
578 ".long loc_FF976EBC\n"
579 ".long loc_FF976EBC\n"
580 ".long loc_FF976EBC\n"
581 ".long loc_FF976D58\n"
582 ".long loc_FF976D64\n"
583 ".long loc_FF976D80\n"
584 ".long loc_FF976D8C\n"
585 ".long loc_FF976DC4\n"
586 ".long loc_FF976DFC\n"
587 ".long loc_FF976E34\n"
588 ".long loc_FF976E6C\n"
589 ".long loc_FF976E6C\n"
590 ".long loc_FF976EBC\n"
591 ".long loc_FF976EBC\n"
592 ".long loc_FF976E78\n"
593 ".long loc_FF976E84\n"
594
595
596 "loc_FF976D34:\n" //@ CODE XREF: task_ExpDrvTask+240
597 "MOV R0, R2\n" //@ Rd = Op2
598 "BL sub_FF972C08\n" //@ Branch with Link
599
600 "B loc_FF976EB8\n" //@ Branch
601
602 "loc_FF976D40:\n" //@ CODE XREF: task_ExpDrvTask+240
603 "MOV R0, R2\n" //@ Rd = Op2
604 "BL sub_FF972EAC\n" //@ Branch with Link
605
606 "B loc_FF976EB8\n" //@ Branch
607
608 "loc_FF976D4C:\n" //@ CODE XREF: task_ExpDrvTask+240
609 "MOV R0, R2\n" //@ Rd = Op2
610 "BL sub_FF973120\n" //@ Branch with Link
611
612 "B loc_FF976EB8\n" //@ Branch
613
614 "loc_FF976D58:\n" //@ CODE XREF: task_ExpDrvTask+240
615 "MOV R0, R2\n" //@ Rd = Op2
616 "BL sub_FF97341C\n" //@ Branch with Link
617
618 "B loc_FF976EB8\n" //@ Branch
619
620 "loc_FF976D64:\n" //@ CODE XREF: task_ExpDrvTask+240
621 "MOV R0, R2\n" //@ Rd = Op2
622 "BL sub_FF973684\n" //@ Branch with Link
623
624 "B loc_FF976EB8\n" //@ Branch
625
626 "loc_FF976D70:\n" //@ CODE XREF: task_ExpDrvTask+240
627 "MOV R0, R2\n" //@ Rd = Op2
628 // "BL sub_FF973980\n" //@ Branch with Link
629 "BL sub_FF973980_my\n" //@ Branch with Link this is the place where the function lies where ewvar also creates its own version of, so we just do the same here
630
631 "MOV R8, #0\n" //@ Rd = Op2
632 "B loc_FF976EB8\n" //@ Branch
633
634 "loc_FF976D80:\n" //@ CODE XREF: task_ExpDrvTask+240
635 "MOV R0, R2\n" //@ Rd = Op2
636 "BL sub_FF973AE0\n" //@ Branch with Link
637
638 "B loc_FF976EB8\n" //@ Branch
639
640
641 "loc_FF976D8C:\n" //@ CODE XREF: task_ExpDrvTask+240
642 "LDRH R1, [R2,#4]\n" //@ Load from Memory
643 // "LDR R3, =0x2E4A8\n" //@ Load from Memory
644 "LDR R3, =0x2E4A8\n" //@ Load from Memory
645 "STRH R1, [SP,#0x14]\n" //@ Store to Memory
646 "LDRH R1, [R3,#6]\n" //@ Load from Memory
647 "STRH R1, [SP,#0x1A]\n" //@ Store to Memory
648 "LDRH R1, [R3,#2]\n" //@ Load from Memory
649 "STRH R1, [SP,#0x16]\n" //@ Store to Memory
650 "LDRH R3, [R3,#4]\n" //@ Load from Memory
651 "STRH R3, [SP,#0x18]\n" //@ Store to Memory
652 "MOV R0, R2\n" //@ Rd = Op2
653 "LDRH R2, [R2,#0xC]\n" //@ Load from Memory
654 "STRH R2, [SP,#0x1C]\n" //@ Store to Memory
655 "BL sub_FF973DDC\n" //@ Branch with Link
656
657 "B loc_FF976EB8\n" //@ Branch
658
659
660 "loc_FF976DC4:\n" //@ CODE XREF: task_ExpDrvTask+240
661 "MOV R0, R2\n" //@ Rd = Op2
662 "LDRH R2, [R2,#4]\n" //@ Load from Memory
663 "LDR R3, =0x2E4A8\n" //@ Load from Memory
664 "STRH R2, [SP,#0x14]\n" //@ Store to Memory
665 "LDRH R2, [R3,#8]\n" //@ Load from Memory
666 "STRH R2, [SP,#0x1C]\n" //@ Store to Memory
667 "LDRH R1, [R3,#2]\n" //@ Load from Memory
668 "STRH R1, [SP,#0x16]\n" //@ Store to Memory
669 "LDRH R2, [R3,#4]\n" //@ Load from Memory
670 "STRH R2, [SP,#0x18]\n" //@ Store to Memory
671 "LDRH R3, [R3,#6]\n" //@ Load from Memory
672 "STRH R3, [SP,#0x1A]\n" //@ Store to Memory
673 "BL sub_FF973F04\n" //@ Branch with Link
674
675 "B loc_FF976EB8\n" //@ Branch
676
677
678 "loc_FF976DFC:\n" //@ CODE XREF: task_ExpDrvTask+240
679 "LDR R3, =0x2E4A8\n" //@ Load from Memory
680 "LDRH R1, [R3]\n" //@ Load from Memory
681 "STRH R1, [SP,#0x14]\n" //@ Store to Memory
682 "MOV R0, R2\n" //@ Rd = Op2
683 "LDRH R2, [R2,#6]\n" //@ Load from Memory
684 "STRH R2, [SP,#0x16]\n" //@ Store to Memory
685 "LDRH R2, [R3,#8]\n" //@ Load from Memory
686 "STRH R2, [SP,#0x1C]\n" //@ Store to Memory
687 "LDRH R1, [R3,#4]\n" //@ Load from Memory
688 "STRH R1, [SP,#0x18]\n" //@ Store to Memory
689 "LDRH R3, [R3,#6]\n" //@ Load from Memory
690 "STRH R3, [SP,#0x1A]\n" //@ Store to Memory
691 "BL sub_FF973FC8\n" //@ Branch with Link
692
693 "B loc_FF976EB8\n" //@ Branch
694
695
696 "loc_FF976E34:\n" //@ CODE XREF: task_ExpDrvTask+240
697 "LDR R3, =0x2E4A8\n" //@ Load from Memory
698 "LDRH R1, [R3,#6]\n" //@ Load from Memory
699 "STRH R1, [SP,#0x1A]\n" //@ Store to Memory
700 "LDRH R1, [R3]\n" //@ Load from Memory
701 "STRH R1, [SP,#0x14]\n" //@ Store to Memory
702 "LDRH R1, [R3,#2]\n" //@ Load from Memory
703 "STRH R1, [SP,#0x16]\n" //@ Store to Memory
704 "LDRH R3, [R3,#4]\n" //@ Load from Memory
705 "STRH R3, [SP,#0x18]\n" //@ Store to Memory
706 "MOV R0, R2\n" //@ Rd = Op2
707 "LDRH R2, [R2,#0xC]\n" //@ Load from Memory
708 "STRH R2, [SP,#0x1C]\n" //@ Store to Memory
709 "BL sub_FF974080\n" //@ Branch with Link
710
711 "B loc_FF976EB8\n" //@ Branch
712
713 "loc_FF976E6C:\n" //@ CODE XREF: task_ExpDrvTask+240
714 "MOV R0, R2\n" //@ Rd = Op2
715 "BL sub_FF974130\n" //@ Branch with Link
716
717 "B loc_FF976EB8\n" //@ Branch
718
719 "loc_FF976E78:\n" //@ CODE XREF: task_ExpDrvTask+240
720 "MOV R0, R2\n" //@ Rd = Op2
721 "BL sub_FF974778\n" //@ Branch with Link
722
723 "B loc_FF976EB8\n" //@ Branch
724
725 "loc_FF976E84:\n" //@ CODE XREF: task_ExpDrvTask+240
726 "MOV R0, R2\n" //@ Rd = Op2
727 "BL sub_FF974A24\n" //@ Branch with Link
728
729 "B loc_FF976EB8\n" //@ Branch
730
731 "loc_FF976E90:\n" //@ CODE XREF: task_ExpDrvTask+240
732 "MOV R0, R2\n" //@ Rd = Op2
733 "BL sub_FF974BE0\n" //@ Branch with Link
734
735 "B loc_FF976EB8\n" //@ Branch
736
737 "loc_FF976E9C:\n" //@ CODE XREF: task_ExpDrvTask+240
738 "MOV R0, R2\n" //@ Rd = Op2
739 "MOV R1, #0\n" //@ Rd = Op2
740 "BL sub_FF974DC8\n" //@ Branch with Link
741
742 "B loc_FF976EB8\n" //@ Branch
743
744 "loc_FF976EAC:\n" //@ CODE XREF: task_ExpDrvTask+240
745 "MOV R0, R2\n" //@ Rd = Op2
746 "MOV R1, #1\n" //@ Rd = Op2
747 "BL sub_FF974DC8\n" //@ Branch with Link
748
749
750 "loc_FF976EB8:\n" //@ CODE XREF: task_ExpDrvTask+2C4
751 "LDR R12, [SP,#0x4]\n" //@ Load from Memory
752
753 "loc_FF976EBC:\n" //@ CODE XREF: task_ExpDrvTask+240
754 "ADD R0, R12, #4\n" //@ Rd = Op1 + Op2
755 "LDR R1, [R12,#0x7C]\n" //@ Load from Memory
756 "LDR R2, [R12,#0x8C]\n" //@ Load from Memory
757 "MOV LR, PC\n" //@ Rd = Op2
758 "LDR PC, [R12,#0x88]\n" //@ Indirect Jump
759
760 "loc_FF976ED0:\n" //@ CODE XREF: task_ExpDrvTask+104
761 "CMP R8, #1\n" //@ Set cond. codes on Op1 - Op2
762 "BNE loc_FF976EF8\n" //@ Branch
763
764 "LDR R1, [SP,#0x4]\n" //@ Load from Memory
765 "LDR R3, [R1,#0x7C]\n" //@ Load from Memory
766 "ADD R3, R3, R3,LSL#1\n" //@ Rd = Op1 + Op2
767 "ADD R1, R1, R3,LSL#2\n" //@ Rd = Op1 + Op2
768 "MOV R0, R6\n" //@ Rd = Op2
769 "SUB R1, R1, #8\n" //@ Rd = Op1 - Op2
770 "BL sub_FF9728C0\n" //@ Branch with Link
771
772 "B loc_FF976F74\n" //@ Branch
773
774
775 "loc_FF976EF8:\n" //@ CODE XREF: task_ExpDrvTask+45C
776 "LDR R3, [SP,#0x4]\n" //@ Load from Memory
777 "LDR R2, [R3]\n" //@ Load from Memory
778 "CMP R2, #9\n" //@ Set cond. codes on Op1 - Op2
779 "BNE loc_FF976F40\n" //@ Branch
780
781 "MOV R4, #0\n" //@ Rd = Op2
782 "MOV R1, #1\n" //@ Rd = Op2
783 "MOV R2, R1\n" //@ Rd = Op2
784 "MOV R3, R1\n" //@ Rd = Op2
785 "MOV R0, R4\n" //@ Rd = Op2
786 "STR R4, [SP]\n" //@ Store to Memory
787 "BL sub_FF972804\n" //@ Branch with Link
788
789 "MOV R1, #1\n" //@ Rd = Op2
790 "MOV R0, R4\n" //@ Rd = Op2
791 "MOV R2, R1\n" //@ Rd = Op2
792 "MOV R3, R1\n" //@ Rd = Op2
793 "STR R4, [SP]\n" //@ Store to Memory
794 "BL sub_FF972A5C\n" //@ Branch with Link
795
796 "B loc_FF976F74\n" //@ Branch
797
798
799 "loc_FF976F40:\n" //@ CODE XREF: task_ExpDrvTask+48C
800 "MOV R4, #1\n" //@ Rd = Op2
801 "MOV R0, R4\n" //@ Rd = Op2
802 "MOV R1, R4\n" //@ Rd = Op2
803 "MOV R2, R4\n" //@ Rd = Op2
804 "MOV R3, R4\n" //@ Rd = Op2
805 "STR R4, [SP]\n" //@ Store to Memory
806 "BL sub_FF972804\n" //@ Branch with Link
807
808 "MOV R0, R4\n" //@ Rd = Op2
809 "MOV R1, R0\n" //@ Rd = Op2
810 "MOV R2, R0\n" //@ Rd = Op2
811 "MOV R3, R0\n" //@ Rd = Op2
812 "STR R4, [SP]\n" //@ Store to Memory
813 "BL sub_FF972A5C\n" //@ Branch with Link
814
815
816 "loc_FF976F74:\n" //@ CODE XREF: task_ExpDrvTask+47C
817 "LDR R2, =0x2E4F4\n" //@ Load from Memory
818 "MOV R3, #0\n" //@ Rd = Op2
819 "LDR R0, [SP,#0x4]\n" //@ Load from Memory
820 "STR R3, [R2]\n" //@ Store to Memory
821 "BL sub_FF9722A8\n" //@ Branch with Link
822
823
824 "loc_FF976F88:\n" //@ CODE XREF: task_ExpDrvTask+C
825 "LDR R3, =0x2E49C\n" //@ Load from Memory
826 "MOV R2, #0\n" //@ Rd = Op2
827 "LDR R0, [R3]\n" //@ Load from Memory
828 "MOV R1, R7\n" //@ Rd = Op2
829 // "BL ReceiveMessageQueue\n" //@ Branch with Link
830 "BL sub_FFB223A8\n" //@ Branch with Link
831
832 "LDR R12, [SP,#0x4]\n" //@ Load from Memory
833 "LDR R2, [R12]\n" //@ Load from Memory
834 "CMP R2, #0x23\n" // @ '#' Set cond. codes on Op1 - Op2
835 "BNE loc_FF976A88\n" //@ Branch
836
837 "MOV R0, R12\n" //@ Rd = Op2
838 "BL sub_FF9722A8\n" //@ Branch with Link
839
840 "LDR R3, =0x2E498\n" //@ Load from Memory
841 "MOV R1, #1\n" //@ Rd = Op2
842 "LDR R0, [R3]\n" //@ Load from Memory
843 // "BL SetEventFlag\n" //@ Branch with Link
844 "BL sub_FFB21C90\n" //@ Branch with Link
845
846 "BL _ExitTask\n" //@ Branch with Link
847
848 "ADD SP, SP, #0x20\n" //@ Rd = Op1 + Op2
849 "LDMFD SP!, {R4-R8,PC}\n" //@ Load Block from Memory
850
851 // "RET\n" //@ Return from Subroutine
852 );
853 }
854
855 void __attribute__((naked,noinline)) sub_FF973980_my() {
856 asm volatile(
857
858 "sub_FF973980:\n" //@ CODE XREF: task_ExpDrvTask+2FC
859 "STMFD SP!, {R4-R6,LR}\n" //@ Store Block to Memory
860 "LDR R3, =0x2E498\n" //@ Load from Memory
861 "MOV R4, R0\n" //@ Rd = Op2
862 "MOV R1, #0x3E\n" // @ '>' Rd = Op2
863 "LDR R0, [R3]\n" //@ Load from Memory
864 // "BL ClearEventFlag\n" //@ Branch with Link
865 "BL sub_FFB21E2C\n" //@ Branch with Link
866
867 "MOV R1, #0\n" //@ Rd = Op2
868 "LDRSH R0, [R4,#4]\n" //@ Load from Memory
869 "BL sub_FF9723DC\n" //@ Branch with Link
870
871 "MOV R6, R0\n" //@ Rd = Op2
872 "LDRSH R0, [R4,#6]\n" //@ Load from Memory
873 "BL sub_FF972544\n" //@ Branch with Link
874
875 "LDRSH R0, [R4,#8]\n" //@ Load from Memory
876 "BL sub_FF9725E0\n" //@ Branch with Link
877
878 "LDRSH R0, [R4,#0xA]\n" //@ Load from Memory
879 "BL sub_FF97267C\n" //@ Branch with Link
880
881 "LDRSH R0, [R4,#0xC]\n" //@ Load from Memory
882 "BL sub_FF972718\n" //@ Branch with Link
883
884 "LDR R3, [R4]\n" //@ Load from Memory
885 "CMP R3, #9\n" //@ Set cond. codes on Op1 - Op2
886 "MOV R5, R0\n" //@ Rd = Op2
887 "MOVEQ R5, #0\n" //@ Rd = Op2
888 "MOVEQ R6, R5\n" //@ Rd = Op2
889 "CMP R6, #1\n" //@ Set cond. codes on Op1 - Op2
890 "BNE loc_FF973A04\n" //@ Branch
891
892 "MOV R2, #2\n" //@ Rd = Op2
893 "LDRSH R0, [R4,#4]\n" //@ Load from Memory
894 // "LDR R1, =loc_FF9722FC\n" //@ Load from Memory
895 "LDR R1, =0xFF9722FC\n" //@ Load from Memory
896 "BL sub_FFAE28F8\n" //@ Branch with Link
897
898 "LDR R2, =0x2E4E8\n" //@ Load from Memory
899 "MOV R3, #0\n" //@ Rd = Op2
900 "STR R3, [R2]\n" //@ Store to Memory
901 "B loc_FF973A08\n" //@ Branch
902
903
904 "loc_FF973A04:\n" //@ CODE XREF: sub_FF973980+60
905 "BL sub_FF9727B4\n" //@ Branch with Link
906
907
908 "loc_FF973A08:\n" //@ CODE XREF: sub_FF973980+80
909 "STRH R0, [R4,#4]\n" //@ Store to Memory
910 "CMP R5, #1\n" //@ Set cond. codes on Op1 - Op2
911 "BNE loc_FF973A28\n" //@ Branch
912
913 "LDRSH R0, [R4,#0xC]\n" //@ Load from Memory
914 // "LDR R1, =loc_FF9723C0\n" //@ Load from Memory
915 "LDR R1, =0xFF9723C0\n" //@ Load from Memory
916 "MOV R2, #0x20\n" // @ ' ' @ Rd = Op2
917 "BL sub_FF972BA8\n" //@ Branch with Link
918
919 "B loc_FF973A2C\n" //@ Branch
920
921 "loc_FF973A28:\n" //@ CODE XREF: sub_FF973980+90
922 "BL sub_FF9727F4\n" //@ Branch with Link
923
924 "loc_FF973A2C:\n" //@ CODE XREF: sub_FF973980+A4
925 "STRH R0, [R4,#0xC]\n" //@ Store to Memory
926 "LDRSH R0, [R4,#6]\n" //@ Load from Memory
927 "BL sub_FF93BD38_my\n" //@ Branch with Link // again an ewvar copy of a function which we also are going to replace
928
929 "LDRSH R0, [R4,#8]\n" //@ Load from Memory
930 "MOV R1, #1\n" //@ Rd = Op2
931 "BL sub_FF93DFEC\n" //@ Branch with Link
932
933 "ADD R0, R4, #8\n" //@ Rd = Op1 + Op2
934 "MOV R1, #0\n" //@ Rd = Op2
935 "BL sub_FF93E0AC\n" //@ Branch with Link
936
937 "LDRSH R0, [R4,#0xE]\n" //@ Load from Memory
938 "BL sub_FF9605D0\n" //@ Branch with Link
939
940 "CMP R6, #1\n" //@ Set cond. codes on Op1 - Op2
941 "BNE loc_FF973A90\n" //@ Branch
942
943 "LDR R3, =0x2E498\n" //@ Load from Memory
944 "MOV R2, #0xBB0\n" //@ Rd = Op2
945 "LDR R0, [R3]\n" //@ Load from Memory
946 "MOV R1, #2\n" //@ Rd = Op2
947 "ADD R2, R2, #8\n" //@ Rd = Op1 + Op2
948 // "BL unknown_libname_854\n" //@ "Canon A-Series Firmware"
949 "BL sub_FFB21C80\n" //@ "Canon A-Series Firmware"
950
951 "TST R0, #1\n" //@ Set cond. codes on Op1 & Op2
952 "BEQ loc_FF973A90\n" //@ Branch
953
954 "MOV R1, #0x500\n" //@ Rd = Op2
955 // "LDR R0, =aExpdrv_c\n" //@ Load from Memory
956 "LDR R0, =0xFF972254\n" //@ Load from Memory => string "ExpDrv.c"
957 "ADD R1, R1, #8\n" //@ Rd = Op1 + Op2
958 // "BL DebugAssert\n" //@ Branch with Link
959 "BL sub_FFB2F4F0\n" //@ Branch with Link
960
961
962 "loc_FF973A90:\n" //@ CODE XREF: sub_FF973980+DC
963 "CMP R5, #1\n" //@ Set cond. codes on Op1 - Op2
964 "LDMNEFD SP!, {R4-R6,PC}\n" //@ Load Block from Memory
965 "LDR R3, =0x2E498\n" //@ Load from Memory
966 "MOV R2, #0xBB0\n" //@ Rd = Op2
967 "LDR R0, [R3]\n" //@ Load from Memory
968 "MOV R1, #0x20\n" // @ ' '\n" //@ Rd = Op2
969 "ADD R2, R2, #8\n" //@ Rd = Op1 + Op2
970 // "BL unknown_libname_854\n" //@ "Canon A-Series Firmware"
971 "BL sub_FFB21C80\n" //@ "Canon A-Series Firmware"
972
973 "TST R0, #1\n" //@ Set cond. codes on Op1 & Op2
974 "LDMEQFD SP!, {R4-R6,PC}\n" //@ Load Block from Memory
975 "MOV R1, #0x500\n" //@ Rd = Op2
976 // "LDR R0, =aExpdrv_c\n" //@ Load from Memory
977 "LDR R0, =0xFF972254\n" //@ Load from Memory
978 "ADD R1, R1, #0xD\n" //@ Rd = Op1 + Op2
979 "LDMFD SP!, {R4-R6,LR}\n" //@ Load Block from Memory
980 // "B DebugAssert\n" //@ Branch
981 "B sub_FFB2F4F0\n" //@ Branch with Link
982
983 );
984 }
985
986 void __attribute__((naked,noinline)) sub_FF93BD38_my(){
987 asm volatile(
988
989
990 "sub_FF93BD38:\n" //@ CODE XREF: sub_FF93D684+Cp
991 "STMFD SP!, {R4,LR}\n" //@ Store Block to Memory
992 // "LDR R3, =unk_6544\n" //@ Load from Memory
993 "LDR R3, =0x6544\n" //@ Load from Memory
994 "LDR R2, [R3]\n" //@ Load from Memory
995 "MOV R1, #0x168\n" //@ Rd = Op2
996 "MOV R3, R0,LSL#16\n" //@ Rd = Op2
997 "CMP R2, #1\n" //@ Set cond. codes on Op1 - Op2
998 "ADD R1, R1, #3\n" //@ Rd = Op1 + Op2
999 // "LDR R0, =aShutter_c\n" //@ Load from Memory => string "Shutter.c"
1000 "LDR R0, =0xFF93B554\n" //@ Load from Memory
1001 "MOV R4, R3,ASR#16\n" //@ Rd = Op2
1002 "BEQ loc_FF93BD64\n" //@ Branch
1003
1004 // "BL DebugAssert\n" //@ Branch with Link
1005 "BL sub_FFB2F4F0\n" //@ Branch with Link
1006
1007
1008 "loc_FF93BD64:\n" //@ CODE XREF: sub_FF93BD38+24j
1009 "MOV R1, #0x170\n" //@ Rd = Op2
1010 "CMN R4, #0xC00\n" //@ Set cond. codes on Op1 + Op2
1011 // "LDR R3, =unk_15036\n" //@ Load from Memory
1012 "LDR R3, =0x15036\n" //@ Load from Memory
1013 // "LDR R0, =aShutter_c\n" //@ Load from Memory
1014 "LDR R0, =0xFF93B554\n" //@ Load from Memory
1015 "ADD R1, R1, #1\n" //@ Rd = Op1 + Op2
1016 "LDREQSH R4, [R3]\n" //@ Load from Memory
1017 "LDRNE R3, =0x15036\n" //@ Load from Memory
1018 "CMN R4, #0xC00\n" //@ Set cond. codes on Op1 + Op2
1019 "STRH R4, [R3]\n" //@ Store to Memory
1020 "BNE loc_FF93BD90\n" //@ Branch
1021
1022 // "BL DebugAssert\n" //@ Branch with Link
1023 "BL sub_FFB2F4F0\n" //@ Branch with Link
1024
1025
1026 "loc_FF93BD90:\n" //@ CODE XREF: sub_FF93BD38+50j
1027 "MOV R0, R4\n" //@ Rd = Op2
1028 // "BL sub_FF93CE88\n" //@ Branch with Link
1029 "BL apex2us\n" //@ Branch with Link => yet another function we need to make our way through to get to our own version
1030
1031 "MOV R4, R0\n" //@ Rd = Op2
1032 // "BL nullsub_118\n" //@ Branch with Link
1033 "BL sub_FF9C2BB0\n" //@ Branch with Link
1034
1035 "MOV R0, R4\n" //@ Rd = Op2
1036 "BL sub_FF9DE41C\n" //@ Branch with Link
1037
1038 "MOV R1, #0x174\n" //@ Rd = Op2
1039 "TST R0, #1\n" //@ Set cond. codes on Op1 & Op2
1040 "ADD R1, R1, #2\n" //@ Rd = Op1 + Op2
1041 // "LDR R0, =aShutter_c\n" //@ Load from Memory
1042 "LDR R0, =0xFF93B554\n" //@ Load from Memory
1043 "LDMEQFD SP!, {R4,PC}\n" //@ Load Block from Memory
1044 "LDMFD SP!, {R4,LR}\n" //@ Load Block from Memory
1045 // "B DebugAssert\n" //@ Branch
1046 "B sub_FFB2F4F0\n" //@ Branch with Link
1047 );
1048 }