1 //code from sx10
2 //adapted to sx110
3
4 #include "conf.h"
5
6 /*void change_video_tables(__attribute__ ((unused))int a, __attribute__ ((unused))int b) {}
7
8
9 void set_quality(int *x){ // -17 highest; +12 lowest
10 if (conf.video_mode) *x=12-((conf.video_quality-1)*(12+17)/(99-1));
11 }
12
13 */
14 int *video_quality = &conf.video_quality;
15 int *video_mode = &conf.video_mode;
16
17 long def_table[24]={0x2000, 0x38D, 0x788, 0x5800, 0x9C5, 0x14B8, 0x10000, 0x1C6A, 0x3C45, 0x8000, 0xE35, 0x1E23,
18 0x1CCD, -0x2E1, -0x579, 0x4F33, -0x7EB, -0xF0C, 0xE666, -0x170A, -0x2BC6, 0x7333, -0xB85, -0x15E3};
19
20 long table[24];
21
22 void change_video_tables(int a, int b){
23 int i;
24 for (i=0;i<24;i++) table[i]=(def_table[i]*a)/b;
25 }
26
27 long CompressionRateTable[]={0x60, 0x5D, 0x5A, 0x57, 0x54, 0x51, 0x4D, 0x48, 0x42, 0x3B, 0x32, 0x29, 0x22, 0x1D, 0x17, 0x14, 0x10, 0xE, 0xB, 9, 7, 6, 5, 4, 3, 2, 1};
28
29
30 //JS
31 void __attribute__((naked,noinline)) movie_record_task(){
32 asm volatile(
33 "STMFD SP!, {R2-R8,LR}\n"
34 "LDR R8, =0x332\n"
35 "LDR R7, =0x2710\n"
36 "LDR R4, =0x5240\n"
37 "MOV R6, #0\n"
38 "MOV R5, #1\n"
39
40 "loc_FFC4CCA4:\n"
41 "LDR R0, [R4,#0x18]\n"
42 "MOV R2, #0\n"
43 "ADD R1, SP, #0x20-0x1c\n"
44 "BL sub_FFC16FF0\n"
45 "LDR R0, [R4,#0x20]\n"
46 "CMP R0, #0\n"
47 "BNE loc_FFC4CD74\n"
48 "LDR R0, [SP,#0x20-0x1c]\n"
49 "LDR R1, [R0]\n"
50 "SUB R1, R1, #2\n"
51 "CMP R1, #9\n"
52 "ADDLS PC, PC, R1,LSL#2\n"
53 "B loc_FFC4CD74\n"
54
55 "loc_FFC4CCD8:\n"
56 "B loc_FFC4CD28\n"
57
58 "loc_FFC4CCDC:\n"
59 "B loc_FFC4CD48\n"
60
61 "loc_FFC4CCE0:\n"
62 "B loc_FFC4CD58\n"
63
64 "loc_FFC4CCE4:\n"
65 "B loc_FFC4CD60\n"
66
67 "loc_FFC4CCE8:\n"
68 "B loc_FFC4CD30\n"
69
70 "loc_FFC4CCEC:\n"
71 "B loc_FFC4CD68\n"
72
73 "loc_FFC4CCF0:\n"
74 "B loc_FFC4CD38\n"
75
76 "loc_FFC4CCF4:\n"
77 "B loc_FFC4CD74\n"
78
79 "loc_FFC4CCF8:\n"
80 "B loc_FFC4CD70\n"
81
82 "loc_FFC4CCFC:\n"
83 "B loc_FFC4CD00\n"
84
85 "loc_FFC4CD00:\n"
86
87 "STR R6, [R4,#0x34]\n"
88 "LDR R0, =0xFFC4C988\n"
89 "LDR R2, =0xFFC4C320\n"
90 "LDR R1, =0x19074\n"
91 "STR R0, [R4,#0xA0]\n"
92 "LDR R0, =0xFFC4C404\n"
93 "STR R6, [R4,#0x24]\n"
94 "BL sub_FFC2A4C0\n"
95 "STR R5, [R4,#0x38]\n"
96 "B loc_FFC4CD74\n"
97
98 "loc_FFC4CD28:\n"
99
100 "BL unlock_optical_zoom\n" // -----------> inserted
101 "BL sub_FFC4CA80\n"
102 "B loc_FFC4CD74\n"
103
104 "loc_FFC4CD30:\n"
105
106
107 "BL sub_0xFFC4C788_my\n" // ------------> changed
108 "B loc_FFC4CD74\n"
109
110 "loc_FFC4CD38:\n"
111
112
113 "LDR R1, [R0,#0x10]\n"
114 "LDR R0, [R0,#4]\n"
115 "BL sub_FFD16958\n"
116 "B loc_FFC4CD74\n"
117
118 "loc_FFC4CD48:\n"
119
120
121 "LDR R0, [R4,#0x38]\n"
122 "CMP R0, #5\n"
123 "STRNE R5, [R4,#0x28]\n"
124 "B loc_FFC4CD74\n"
125
126 "loc_FFC4CD58:\n"
127
128
129 "BL sub_FFC4C594\n"
130 "B loc_FFC4CD74\n"
131
132 "loc_FFC4CD60:\n"
133
134
135 "BL sub_FFC4C450\n"
136 "B loc_FFC4CD74\n"
137
138 "loc_FFC4CD68:\n"
139
140
141 "BL sub_FFC4C2AC\n"
142 "B loc_FFC4CD74\n"
143
144 "loc_FFC4CD70:\n"
145
146
147 "BL sub_FFC4CEDC\n"
148
149 "loc_FFC4CD74:\n"
150
151
152
153 "LDR R1, [SP,#0x20-0x1C]\n"
154 "LDR R3, =0xFFC4C10C\n"
155 "STR R6, [R1]\n"
156 "STR R8, [SP,#0x20-0x20]\n"
157 "LDR R0, [R4,#0x1C]\n"
158 "MOV R2, R7\n"
159 "BL sub_FFC0BCD8\n"
160 "B loc_FFC4CCA4\n"
161 );
162 }
163 //JSE
164
165 void __attribute__((naked,noinline)) sub_0xFFC4C788_my(){
166 asm volatile(
167 "STMFD SP!, {R4-R8,LR}\n"
168 "SUB SP, SP, #0x40\n"
169 "MOV R6, #0\n"
170 "LDR R5, =0x5240\n"
171 "MOV R4, R0\n"
172 "STR R6, [SP,#0x58-0x28]\n"
173 "STR R6, [SP,#0x58-0x30]\n"
174 "LDR R0, [R5,#0x38]\n"
175 "MOV R8, #4\n"
176 "CMP R0, #3\n"
177 "STREQ R8, [R5,#0x38]\n"
178 "LDR R0, [R5,#0xA0]\n"
179 // "BLX R0\n" // !! Workaround !!
180 "MOV LR, PC\n" // gcc won't compile "BLX R0" nor "BL R0".
181 "MOV PC, R0\n" // workaround: make your own "BL" and hope we don't need the change to thumb-mode
182
183 "LDR R0, [R5,#0x38]\n"
184 "CMP R0, #4\n"
185 "BNE loc_FFC4C860\n"
186 "ADD R3, SP, #0x58-0x30\n"
187 "ADD R2, SP, #0x58-0x30+4\n"
188 "ADD R1, SP, #0x58-0x28\n"
189 "ADD R0, SP, #0x58-0x24\n"
190 "BL sub_FFD16AEC\n"
191 "CMP R0, #0\n"
192 "MOV R7, #1\n"
193 "BNE loc_FFC4C804\n"
194 "LDR R1, [R5,#0x28]\n"
195 "CMP R1, #1\n"
196 "BNE loc_FFC4C868\n"
197 "LDR R1, [R5,#0x50]\n"
198 "LDR R2, [R5,#0x3C]\n"
199 "CMP R1, R2\n"
200 "BCC loc_FFC4C868\n"
201
202 "loc_FFC4C804:\n"
203 "CMP R0, #0x80000001\n"
204 "STREQ R8, [R5,#0x54]\n"
205 "BEQ loc_FFC4C83C\n"
206 "CMP R0, #0x80000003\n"
207 "STREQ R7, [R5,#0x54]\n"
208 "BEQ loc_FFC4C83C\n"
209 "CMP R0, #0x80000005\n"
210 "MOVEQ R0, #2\n"
211 "BEQ loc_FFC4C838\n"
212 "CMP R0, #0x80000007\n"
213 "STRNE R6, [R5,#0x54]\n"
214 "BNE loc_FFC4C83C\n"
215 "MOV R0, #3\n"
216
217 "loc_FFC4C838:\n"
218 "STR R0, [R5,#0x54]\n"
219
220 "loc_FFC4C83C:\n"
221
222 "LDR R0, =0x190A4\n"
223 "LDR R0, [R0,#8]\n"
224 "CMP R0, #0\n"
225 "BEQ loc_FFC4C854\n"
226 "BL sub_FFC37750\n"
227 "B loc_FFC4C858\n"
228
229 "loc_FFC4C854:\n"
230 "BL sub_FFC4C2AC\n"
231
232 "loc_FFC4C858:\n"
233 "MOV R0, #5\n"
234 "STR R0, [R5,#0x38]\n"
235
236 "loc_FFC4C860:\n"
237
238 "ADD SP, SP, #0x40\n"
239 "LDMFD SP!, {R4-R8,PC}\n"
240
241 "loc_FFC4C868:\n"
242
243 "LDR LR, [SP,#0x58-0x28]\n"
244 "CMP LR, #0\n"
245 "BEQ loc_FFC4C930\n"
246 "STR R7, [R5,#0x2C]\n"
247 "LDR R0, [R5,#0x6C]\n"
248 "LDR R1, [R4,#0x14]\n"
249 "LDR R2, [R4,#0x18]\n"
250 "LDR R12, [R4,#0xC]\n"
251 "ADD R3, SP, #0x58-0x20\n"
252 "ADD R8, SP, #0x58-0x44\n"
253 "STMIA R8, {R0-R3}\n"
254 "LDR R3, [R5,#0x58]\n"
255 "ADD R2, SP, #0x58-0x1C\n"
256 "ADD R8, SP, #0x58-0x50\n"
257
258 // "LDRD R0, [SP,#0x58-0x30]\n" //Workaround, selected processor does not support `ldrd R0,[SP,#0x58-0x30]'
259 ".long 0xE1CD02D8\n" //binary representation of instruction above
260
261 "STMIA R8, {R0,R2,R3}\n"
262 "STR R1, [SP,#0x58-0x54]\n"
263 "STR LR, [SP,#0x58-0x58]\n"
264 "LDMIB R4, {R0,R1}\n"
265 "LDR R3, [SP,#0x58-0x24]\n"
266 "MOV R2, R12\n"
267 "BL sub_FFCDBF24\n"
268 "LDR R0, [R5,#0x10]\n"
269 "MOV R1, #0x3E8\n"
270 "BL sub_FFC0B74C \n"
271 "CMP R0, #9\n"
272 "BNE loc_FFC4C8E4\n"
273 "BL sub_FFD170C8\n"
274 "MOV R0, #0x90000\n"
275 "STR R7, [R5,#0x38]\n"
276 "B loc_FFC4C8FC\n"
277
278 "loc_FFC4C8E4:\n"
279 "LDR R0, [SP,#0x58-0x20]\n"
280 "CMP R0, #0\n"
281 "BEQ loc_FFC4C904\n"
282 "BL sub_FFD170C8\n"
283 "MOV R0, #0xA0000\n"
284 "STR R7, [R5,#0x38]\n"
285
286 "loc_FFC4C8FC:\n"
287 "BL sub_FFC6403C\n"
288 "B loc_FFC4C860\n"
289
290 "loc_FFC4C904:\n"
291 "BL sub_FFCDBFE8\n"
292 "LDR R0, [SP,#0x58-0x24]\n"
293 "LDR R1, [SP,#0x58-0x1C]\n"
294 "BL sub_FFD16E70\n"
295 "LDR R0, [R5,#0x4C]\n"
296 "LDR R1, =0x52AC\n" //-------> see later
297 "ADD R0, R0, #1\n"
298 "STR R0, [R5,#0x4C]\n"
299 "LDR R0, [SP,#0x58-0x1C]\n"
300 "MOV R2, #0\n"
301
302 "BL sub_FFD14CE8_my\n"
303
304 // "BL sub_FFD14CE8\n"
305
306 // "LDR R0, =0x52AC\n" // -<---- // inserted
307 // "BL set_quality\n" // inserted
308
309 "loc_FFC4C930:\n"
310 "LDR R0, [R5,#0x50]\n"
311 "ADD R0, R0, #1\n"
312 "STR R0, [R5,#0x50]\n"
313 "LDR R1, [R5,#0x78]\n"
314 "MUL R0, R1, R0\n"
315 "LDR R1, [R5,#0x74]\n"
316 "BL sub_FFE90A04\n"
317 "MOV R4, R0\n"
318 "BL sub_FFD17100\n"
319 "LDR R1, [R5,#0x70]\n"
320 "CMP R1, R4\n"
321 "BNE loc_FFC4C96C\n"
322 "LDR R0, [R5,#0x30]\n"
323 "CMP R0, #1\n"
324 "BNE loc_FFC4C980\n"
325
326 "loc_FFC4C96C:\n"
327 "LDR R1, [R5,#0x84]\n"
328 "MOV R0, R4\n"
329 // "BLX R1\n" // !! Workaround !!
330 "MOV LR, PC\n" // gcc won't compile "BLX R1" nor "BL R1".
331 "MOV PC, R1\n" // workaround: make your own "BL" and hope we don't need the change to thumb-mode
332
333 "STR R4, [R5,#0x70]\n"
334 "STR R6, [R5,#0x30]\n"
335
336 "loc_FFC4C980:\n"
337 "STR R6, [R5,#0x2C]\n"
338 "B loc_FFC4C860\n"
339 );
340 }
341
342 void __attribute__((naked,noinline)) sub_FFD14CE8_my(){
343 asm volatile(
344 "STMFD SP!, {R4-R8,LR} \n"
345 "LDR R4, =0x8764 \n"
346 "LDR LR, [R4] \n"
347 "LDR R2, [R4,#8] \n"
348 "CMP LR, #0 \n"
349 "LDRNE R3, [R4,#0xC] \n"
350 "MOV R5, R2 \n"
351 "CMPNE R3, #1 \n"
352 "MOVEQ R2, #0 \n"
353 "STREQ R0, [R4] \n"
354 "STREQ R2, [R4,#0xC] \n"
355 "BEQ loc_FFD14DB4 \n"
356 "LDR R3, [R4,#4] \n"
357 // "LDR R7, =0xFFEB2548 \n"
358 "LDR R7, =table\n" // -----> changed
359 "ADD R12, R3, R3,LSL#1 \n"
360 "LDR R3, [R7,R12,LSL#2] \n"
361 "ADD R6, R7, #0x30 \n"
362 "LDR R8, [R6,R12,LSL#2] \n"
363 "SUB R3, LR, R3 \n"
364 "CMP R3, #0 \n"
365 "SUB LR, LR, R8 \n"
366 "BLE loc_FFD14D70 \n"
367 "ADD R12, R7, R12,LSL#2 \n"
368 "LDR LR, [R12,#4] \n"
369 "CMP LR, R3 \n"
370 "ADDGE R2, R2, #1 \n"
371 "BGE loc_FFD14D64 \n"
372 "LDR R12, [R12,#8] \n"
373 "CMP R12, R3 \n"
374 "ADDLT R2, R2, #3 \n"
375 "ADDGE R2, R2, #2 \n"
376
377 "loc_FFD14D64:\n"
378 // "CMP R2, #0x17 \n"
379 // "MOVGE R2, #0x16 \n"
380 "CMP R2, #0x1A\n" // ---------> changed
381 "MOVGE R2, #0x19\n" // ---------> changed
382 "B loc_FFD14DA4 \n"
383
384 "loc_FFD14D70:\n"
385 "CMP LR, #0 \n"
386 "BGE loc_FFD14DA4 \n"
387 "ADD R3, R6, R12,LSL#2 \n"
388 "LDR R12, [R3,#4] \n"
389 "CMP R12, LR \n"
390 "SUBLE R2, R2, #1 \n"
391 "BLE loc_FFD14D9C \n"
392 "LDR R3, [R3,#8] \n"
393 "CMP R3, LR \n"
394 "SUBGT R2, R2, #3 \n"
395 "SUBLE R2, R2, #2 \n"
396
397 "loc_FFD14D9C:\n"
398 "CMP R2, #0 \n"
399 "MOVLT R2, #0 \n"
400
401 "loc_FFD14DA4:\n"
402
403 "CMP R2, R5 \n"
404 "STRNE R2, [R4,#8] \n"
405 "MOVNE R2, #1 \n"
406 "STRNE R2, [R4,#0xC] \n"
407
408 "loc_FFD14DB4:\n"
409 // "LDR R2, =0xFFEB24EC \n"
410 "LDR R2, =CompressionRateTable\n" //----------> changed
411 "LDR R3, [R4,#8] \n"
412 "LDR R2, [R2,R3,LSL#2] \n"
413
414 "LDR R3, =video_mode\n" // --------> inserted
415 "LDR R3, [R3]\n" // --------> inserted
416 "LDR R3, [R3]\n" // --------> inserted
417 "CMP R3, #1\n" // --------> inserted
418 "LDREQ R3, =video_quality\n" // --------> inserted
419 "LDREQ R3, [R3]\n" // --------> inserted
420 "LDREQ R2, [R3]\n" // --------> inserted
421
422 "STR R2, [R1] \n"
423 "STR R0, [R4] \n"
424
425 "BL mute_on_zoom\n" // --------> inserted
426
427 "LDMFD SP!, {R4-R8,PC} \n"
428 );
429 }