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cpuinfo_v7.c-Dateireferenz

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Funktionen

static const char * two_on_nth (unsigned val)
 
static const char * two_on_nth_granule (unsigned val)
 
static const char * ctype_str (unsigned val)
 
static const char * ccsidr_linesize (unsigned val)
 
static const char * ccsidr_plusone (unsigned val)
 
static const char * cache_tcm_size_str (unsigned val)
 
static const char * cache_tcm_addr_str (unsigned val)
 
static const char * mpu_region_size_str (unsigned val)
 
static const char * bitfield8 (unsigned val)
 
static const char * mpu_rattr (unsigned val)
 
static const char * dbg_version (unsigned val)
 
void __attribute__ ((naked, noinline))
 

Variablen

static char linebuf [128]
 
static const char * two_nth_str []
 
struct cpuinfo_bitfield_desc_s cpuinf_feat0 []
 
struct cpuinfo_bitfield_desc_s cpuinf_feat1 []
 
struct cpuinfo_bitfield_desc_s cpuinf_mmfr0 []
 
struct cpuinfo_bitfield_desc_s cpuinf_mmfr1 []
 
struct cpuinfo_bitfield_desc_s cpuinf_mmfr2 []
 
struct cpuinfo_bitfield_desc_s cpuinf_mmfr3 []
 
struct cpuinfo_bitfield_desc_s cpuinf_isar0 []
 
struct cpuinfo_bitfield_desc_s cpuinf_isar1 []
 
struct cpuinfo_bitfield_desc_s cpuinf_isar2 []
 
struct cpuinfo_bitfield_desc_s cpuinf_isar3 []
 
struct cpuinfo_bitfield_desc_s cpuinf_isar4 []
 
struct cpuinfo_bitfield_desc_s cpuinf_isar5 []
 
struct cpuinfo_bitfield_desc_s cpuinf_ctr []
 
struct cpuinfo_bitfield_desc_s cpuinf_clidr []
 
struct cpuinfo_bitfield_desc_s cpuinf_csselr []
 
struct cpuinfo_bitfield_desc_s cpuinf_ccsidr []
 
struct cpuinfo_bitfield_desc_s cpuinf_tcmreg []
 
struct cpuinfo_bitfield_desc_s cpuinf_mputype []
 
struct cpuinfo_bitfield_desc_s cpuinf_mpubase []
 
struct cpuinfo_bitfield_desc_s cpuinf_sctlr []
 
struct cpuinfo_bitfield_desc_s cpuinf_mpusizeen []
 
struct cpuinfo_bitfield_desc_s cpuinf_accesscontrol []
 
struct cpuinfo_bitfield_desc_s cpuinf_generic []
 
static struct
cpuinfo_bitfield_desc_s 
cpuinf_dbgdidr []
 
static struct
cpuinfo_bitfield_desc_s 
cpuinf_dbgd_address []
 
static struct
cpuinfo_bitfield_desc_s 
cpuinf_dbgdscr []
 
struct cpuinfo_word_desc_s cpuinfo_desc []
 

Dokumentation der Funktionen

void __attribute__ ( (naked, noinline)  )

Definiert in Zeile 488 der Datei cpuinfo_v7.c.

488  {
489  asm (
490  ".syntax unified\n"
491  ".code 16\n"
492  ".align 2\n"
493  "BX PC\n" // switch to ARM mode
494  ".code 32\n"
495 
496  "MRC p15, 0, R1,c0,c0\n" // ident
497  "STR R1, [R0]\n"
498 
499  "MRC p15, 0, R1,c0,c0,1\n" // cache
500  "ADD R0, R0, #4\n"
501  "STR R1, [R0]\n"
502 
503  "MRC p15, 0, R1,c0,c0,2\n" // TCM
504  "ADD R0, R0, #4\n"
505  "STR R1, [R0]\n"
506 
507  "MRC p15, 0, R1,c0,c0,4\n" // MPU
508  "ADD R0, R0, #4\n"
509  "STR R1, [R0]\n"
510 
511  "MRC p15, 0, R1,c0,c0,5\n" // MPIDR
512  "ADD R0, R0, #4\n"
513  "STR R1, [R0]\n"
514 
515  "MRC p15, 0, R1,c0,c1,0\n" // ID_PFR0
516  "ADD R0, R0, #4\n"
517  "STR R1, [R0]\n"
518 
519  "MRC p15, 0, R1,c0,c1,1\n" // ID_PFR1
520  "ADD R0, R0, #4\n"
521  "STR R1, [R0]\n"
522 
523  "MRC p15, 0, R1,c0,c1,2\n" // ID_DFR0
524  "ADD R0, R0, #4\n"
525  "STR R1, [R0]\n"
526 
527  "MRC p15, 0, R1,c0,c1,3\n" // ID_AFR0
528  "ADD R0, R0, #4\n"
529  "STR R1, [R0]\n"
530 
531  "MRC p15, 0, R1,c0,c1,4\n" // ID_MMFR0
532  "ADD R0, R0, #4\n"
533  "STR R1, [R0]\n"
534 
535  "MRC p15, 0, R1,c0,c1,5\n" // ID_MMFR1
536  "ADD R0, R0, #4\n"
537  "STR R1, [R0]\n"
538 
539  "MRC p15, 0, R1,c0,c1,6\n" // ID_MMFR2
540  "ADD R0, R0, #4\n"
541  "STR R1, [R0]\n"
542 
543  "MRC p15, 0, R1,c0,c1,7\n" // ID_MMFR3
544  "ADD R0, R0, #4\n"
545  "STR R1, [R0]\n"
546 
547  "MRC p15, 0, R1,c0,c2,0\n" // ID_ISAR0
548  "ADD R0, R0, #4\n"
549  "STR R1, [R0]\n"
550 
551  "MRC p15, 0, R1,c0,c2,1\n" // ID_ISAR1
552  "ADD R0, R0, #4\n"
553  "STR R1, [R0]\n"
554 
555  "MRC p15, 0, R1,c0,c2,2\n" // ID_ISAR2
556  "ADD R0, R0, #4\n"
557  "STR R1, [R0]\n"
558 
559  "MRC p15, 0, R1,c0,c2,3\n" // ID_ISAR3
560  "ADD R0, R0, #4\n"
561  "STR R1, [R0]\n"
562 
563  "MRC p15, 0, R1,c0,c2,4\n" // ID_ISAR4
564  "ADD R0, R0, #4\n"
565  "STR R1, [R0]\n"
566 
567  "MRC p15, 0, R1,c0,c2,5\n" // ID_ISAR5
568  "ADD R0, R0, #4\n"
569  "STR R1, [R0]\n"
570 
571  "MRC p15, 1, R1,c0,c0,1\n" // CLIDR
572  "ADD R0, R0, #4\n"
573  "STR R1, [R0]\n"
574 
575  "MOV R1, #0\n"
576  "MCR p15, 2, R1,c0,c0,0\n" // CSSELR (data cache, level0)
577 
578  "MRC p15, 1, R1,c0,c0,0\n" // CCSIDR (the currently selected one)
579  "ADD R0, R0, #4\n"
580  "STR R1, [R0]\n"
581 
582  "MOV R1, #1\n"
583  "MCR p15, 2, R1,c0,c0,0\n" // CSSELR (inst cache, level0)
584 
585  "MRC p15, 1, R1,c0,c0,0\n" // CCSIDR (the currently selected one)
586  "ADD R0, R0, #4\n"
587  "STR R1, [R0]\n"
588 
589  "MRC p15, 0, R1,c1,c0,0\n" // SCTLR
590  "ADD R0, R0, #4\n"
591  "STR R1, [R0]\n"
592 
593  "MRC p15, 0, R1,c1,c0,1\n" // ACTLR
594  "ADD R0, R0, #4\n"
595  "STR R1, [R0]\n"
596 
597 //#ifndef CONFIG_QEMU
598  "MRC p15, 0, R1,c15,c0,0\n" // ACTLR2
599  "ADD R0, R0, #4\n"
600  "STR R1, [R0]\n"
601 //#endif
602 
603  "MRC p15, 0, R1,c1,c0,2\n" // CPACR
604  "ADD R0, R0, #4\n"
605  "STR R1, [R0]\n"
606 
607  "MRC p15, 0, R1,c15,c2,0\n" // Build options 1 reg
608  "ADD R0, R0, #4\n"
609  "STR R1, [R0]\n"
610 
611  "MRC p15, 0, R1,c15,c2,1\n" // Build options 2 reg
612  "ADD R0, R0, #4\n"
613  "STR R1, [R0]\n"
614 
615  "MRC p15, 0, R1,c9,c1,1\n" // ATCM region reg
616  "ADD R0, R0, #4\n"
617  "STR R1, [R0]\n"
618 
619  "MRC p15, 0, R1,c9,c1,0\n" // BTCM region reg
620  "ADD R0, R0, #4\n"
621  "STR R1, [R0]\n"
622 
623  "MOV R1, #0\n"
624  "MCR p15, 0, R1,c6,c2,0\n" // MPU Memory Region Number Register, region 0
625 
626  "MRC p15, 0, R1,c6,c1,0\n" // MPU region base register
627  "ADD R0, R0, #4\n"
628  "STR R1, [R0]\n"
629  "MRC p15, 0, R1,c6,c1,2\n" // MPU Region Size and Enable Register
630  "ADD R0, R0, #4\n"
631  "STR R1, [R0]\n"
632  "MRC p15, 0, R1,c6,c1,4\n" // MPU Region Access Control Register
633  "ADD R0, R0, #4\n"
634  "STR R1, [R0]\n"
635 
636  "MOV R1, #1\n"
637  "MCR p15, 0, R1,c6,c2,0\n" // region 1
638 
639  "MRC p15, 0, R1,c6,c1,0\n" // MPU region base register
640  "ADD R0, R0, #4\n"
641  "STR R1, [R0]\n"
642  "MRC p15, 0, R1,c6,c1,2\n" // MPU Region Size and Enable Register
643  "ADD R0, R0, #4\n"
644  "STR R1, [R0]\n"
645  "MRC p15, 0, R1,c6,c1,4\n" // MPU Region Access Control Register
646  "ADD R0, R0, #4\n"
647  "STR R1, [R0]\n"
648 
649  "MOV R1, #2\n"
650  "MCR p15, 0, R1,c6,c2,0\n" // region 2
651 
652  "MRC p15, 0, R1,c6,c1,0\n" // MPU region base register
653  "ADD R0, R0, #4\n"
654  "STR R1, [R0]\n"
655  "MRC p15, 0, R1,c6,c1,2\n" // MPU Region Size and Enable Register
656  "ADD R0, R0, #4\n"
657  "STR R1, [R0]\n"
658  "MRC p15, 0, R1,c6,c1,4\n" // MPU Region Access Control Register
659  "ADD R0, R0, #4\n"
660  "STR R1, [R0]\n"
661 
662  "MOV R1, #3\n"
663  "MCR p15, 0, R1,c6,c2,0\n" // region 3
664 
665  "MRC p15, 0, R1,c6,c1,0\n" // MPU region base register
666  "ADD R0, R0, #4\n"
667  "STR R1, [R0]\n"
668  "MRC p15, 0, R1,c6,c1,2\n" // MPU Region Size and Enable Register
669  "ADD R0, R0, #4\n"
670  "STR R1, [R0]\n"
671  "MRC p15, 0, R1,c6,c1,4\n" // MPU Region Access Control Register
672  "ADD R0, R0, #4\n"
673  "STR R1, [R0]\n"
674 
675  "MOV R1, #4\n"
676  "MCR p15, 0, R1,c6,c2,0\n" // region 4
677 
678  "MRC p15, 0, R1,c6,c1,0\n" // MPU region base register
679  "ADD R0, R0, #4\n"
680  "STR R1, [R0]\n"
681  "MRC p15, 0, R1,c6,c1,2\n" // MPU Region Size and Enable Register
682  "ADD R0, R0, #4\n"
683  "STR R1, [R0]\n"
684  "MRC p15, 0, R1,c6,c1,4\n" // MPU Region Access Control Register
685  "ADD R0, R0, #4\n"
686  "STR R1, [R0]\n"
687 
688  "MOV R1, #5\n"
689  "MCR p15, 0, R1,c6,c2,0\n" // region 5
690 
691  "MRC p15, 0, R1,c6,c1,0\n" // MPU region base register
692  "ADD R0, R0, #4\n"
693  "STR R1, [R0]\n"
694  "MRC p15, 0, R1,c6,c1,2\n" // MPU Region Size and Enable Register
695  "ADD R0, R0, #4\n"
696  "STR R1, [R0]\n"
697  "MRC p15, 0, R1,c6,c1,4\n" // MPU Region Access Control Register
698  "ADD R0, R0, #4\n"
699  "STR R1, [R0]\n"
700 
701  "MOV R1, #6\n"
702  "MCR p15, 0, R1,c6,c2,0\n" // region 6
703 
704  "MRC p15, 0, R1,c6,c1,0\n" // MPU region base register
705  "ADD R0, R0, #4\n"
706  "STR R1, [R0]\n"
707  "MRC p15, 0, R1,c6,c1,2\n" // MPU Region Size and Enable Register
708  "ADD R0, R0, #4\n"
709  "STR R1, [R0]\n"
710  "MRC p15, 0, R1,c6,c1,4\n" // MPU Region Access Control Register
711  "ADD R0, R0, #4\n"
712  "STR R1, [R0]\n"
713 
714  "MOV R1, #7\n"
715  "MCR p15, 0, R1,c6,c2,0\n" // region 7
716 
717  "MRC p15, 0, R1,c6,c1,0\n" // MPU region base register
718  "ADD R0, R0, #4\n"
719  "STR R1, [R0]\n"
720  "MRC p15, 0, R1,c6,c1,2\n" // MPU Region Size and Enable Register
721  "ADD R0, R0, #4\n"
722  "STR R1, [R0]\n"
723  "MRC p15, 0, R1,c6,c1,4\n" // MPU Region Access Control Register
724  "ADD R0, R0, #4\n"
725  "STR R1, [R0]\n"
726 
727  "MRC p14, 0, R1,c0,c0,0\n" // DBGDIDR
728  "ADD R0, R0, #4\n"
729  "STR R1, [R0]\n"
730 
731  "MRC p14, 0, R1,c1,c0,0\n" // DBGDRAR
732  "ADD R0, R0, #4\n"
733  "STR R1, [R0]\n"
734 
735  "MRC p14, 0, R1,c2,c0,0\n" // DBGDSAR
736  "ADD R0, R0, #4\n"
737  "STR R1, [R0]\n"
738 
739  "MRC p14, 0, R1,c0,c1,0\n" // DBGDSCR
740  "ADD R0, R0, #4\n"
741  "STR R1, [R0]\n"
742 
743  //".word 0xEEF01A10\n" //"VMRS R1, FPSID\n" // Floating Point System ID register
744  //"ADD R0, R0, #4\n"
745  //"STR R1, [R0]\n"
746 
747  //".word 0xEEF71A10\n" //"VMRS R1, MVFR0\n" // Media and VFP Feature Register 0
748  //"ADD R0, R0, #4\n"
749  //"STR R1, [R0]\n"
750 
751  //".word 0xEEF61A10\n" //"VMRS R1, MVFR1\n" // Media and VFP Feature Register 1
752  //"ADD R0, R0, #4\n"
753  //"STR R1, [R0]\n"
754 
755  "BX LR\n"
756 
757  :::"r0","r1"
758  );
759 }
static const char* bitfield8 ( unsigned  val)
static

Definiert in Zeile 292 der Datei cpuinfo_v7.c.

292  {
293  linebuf[8] = 0;
294  int n;
295  for (n=0; n<8; n++) {
296  linebuf[7-n] = (val & (1<<n))?'1':'0';
297  }
298  return linebuf;
299 }
static const char* cache_tcm_addr_str ( unsigned  val)
static

Definiert in Zeile 229 der Datei cpuinfo_v7.c.

229  {
230  sprintf(linebuf,"0x%08x",val<<12);
231  return linebuf;
232 }
static const char* cache_tcm_size_str ( unsigned  val)
static

Definiert in Zeile 221 der Datei cpuinfo_v7.c.

221  {
222  if (val == 0)
223  return "0";
224  if (val < 3 || val > 14)
225  return "invalid";
226  return reg_sizes[val-3];
227 }
static const char* ccsidr_linesize ( unsigned  val)
static

Definiert in Zeile 201 der Datei cpuinfo_v7.c.

201  {
202  return two_nth_str[val+2];
203 }
static const char* ccsidr_plusone ( unsigned  val)
static

Definiert in Zeile 205 der Datei cpuinfo_v7.c.

205  {
206  sprintf(linebuf,"%i",val+1);
207  return linebuf;
208 }
static const char* ctype_str ( unsigned  val)
static

Definiert in Zeile 168 der Datei cpuinfo_v7.c.

168  {
169  switch (val) {
170  case 0: return "no cache";
171  case 1: return "Icache only";
172  case 2: return "Dcache only";
173  case 3: return "Separate Icache, Dcache";
174  case 4: return "Unified cache";
175  }
176  return "-";
177 }
static const char* dbg_version ( unsigned  val)
static

Definiert in Zeile 359 der Datei cpuinfo_v7.c.

359  {
360  switch(val) {
361  case 0b0001: return "v6";
362  case 0b0010: return "v6.1";
363  case 0b0011: return "v7 full";
364  case 0b0100: return "v7 basic";
365  case 0b0101: return "v7.1";
366  case 0b0110: return "v8";
367  case 0b0111: return "v8.1";
368  case 0b1000: return "v8.2";
369  }
370  return "???";
371 }
static const char* mpu_rattr ( unsigned  val)
static

Definiert in Zeile 309 der Datei cpuinfo_v7.c.

309  {
310  char *s="";
311  char *s2="";
312  char *t;
313  t = (val&4)?"Shared":"Non-shared";
314  if (val&0x20) {
315  switch (val&3) {
316  case 0: s = "Inner Non-cacheable"; break;
317  case 1: s = "Inner Write-back, write-allocate"; break;
318  case 2: s = "Inner Write-through, no write-allocate"; break;
319  case 3: s = "Inner Write-back, no write-allocate"; break;
320  }
321  switch ((val&0x18)>>3) {
322  case 0: s2 = "Outer Non-cacheable"; break;
323  case 1: s2 = "Outer Write-back, write-allocate"; break;
324  case 2: s2 = "Outer Write-through, no write-allocate"; break;
325  case 3: s2 = "Outer Write-back, no write-allocate"; break;
326  }
327  sprintf(linebuf,"%s; %s; %s",s, s2, t);
328  }
329  else {
330  switch (val&0x1B) {
331  case 0: s = "Strongly ordered, shareable"; t=""; break;
332  case 1: s = "Shareable device"; t="Shareable"; break;
333  case 2: s = "Outer and Inner write-through, no write-allocate"; break;
334  case 3: s = "Outer and Inner write-back, no write-allocate"; break;
335  case 8: s = "Outer and Inner Non-cacheable"; break;
336  case 11: s = "Outer and Inner write-back, write-allocate"; break;
337  case 16: s = "Non-shareable Device"; t=""; break;
338  default: s = "(reserved)"; t="";
339  }
340  sprintf(linebuf,"%s; %s",s, t);
341  }
342  return linebuf;
343 }
static const char* mpu_region_size_str ( unsigned  val)
static

Definiert in Zeile 284 der Datei cpuinfo_v7.c.

284  {
285  if (val < 4 || val > 31)
286  return "invalid";
287  if (val < 11)
288  return two_nth_str[val+1];
289  return reg_sizes[val-11];
290 }
static const char* two_on_nth ( unsigned  val)
static

Definiert in Zeile 9 der Datei cpuinfo_v7.c.

9  {
10  if (val < 16) {
11  return two_nth_str[val];
12  }
13  return "invalid";
14 }
static const char* two_on_nth_granule ( unsigned  val)
static

Definiert in Zeile 16 der Datei cpuinfo_v7.c.

16  {
17  if (val == 0) {
18  return "no info";
19  }
20  else if (val > 9) {
21  return "reserved";
22  }
23  else {
24  return two_nth_str[val];
25  }
26  return "invalid";
27 }

Variablen-Dokumentation

struct cpuinfo_bitfield_desc_s cpuinf_accesscontrol[]
Initialisierung:
= {
{6,"Region attributes", mpu_rattr},
{2,"-"},
{3,"Access permission", regperm_str},
{1,"-"},
{1,"Execute never"},
{}
}

Definiert in Zeile 345 der Datei cpuinfo_v7.c.

struct cpuinfo_bitfield_desc_s cpuinf_ccsidr[]
Initialisierung:
= {
{3,"Line size in words", ccsidr_linesize},
{10,"Associativity", ccsidr_plusone},
{15,"Number of sets", ccsidr_plusone},
{1,"Write allocation"},
{1,"Read allocation"},
{1,"Write back"},
{1,"Write through"},
{}
}

Definiert in Zeile 210 der Datei cpuinfo_v7.c.

struct cpuinfo_bitfield_desc_s cpuinf_clidr[]
Initialisierung:
= {
{3,"Cache type, level1", ctype_str},
{3,"Cache type, level2", ctype_str},
{3,"Cache type, level3", ctype_str},
{3,"Cache type, level4", ctype_str},
{3,"Cache type, level5", ctype_str},
{3,"Cache type, level6", ctype_str},
{3,"Cache type, level7", ctype_str},
{3,"Cache type, level8", ctype_str},
{3,"Level of coherency"},
{3,"Level of unification"},
{2,"(zero)"},
{}
}

Definiert in Zeile 179 der Datei cpuinfo_v7.c.

struct cpuinfo_bitfield_desc_s cpuinf_csselr[]
Initialisierung:
= {
{1,"Instruction, not data"},
{3,"Level"},
{28,"(unknown)"},
{}
}

Definiert in Zeile 194 der Datei cpuinfo_v7.c.

struct cpuinfo_bitfield_desc_s cpuinf_ctr[]
Initialisierung:
= {
{4,"Icache min words/line", two_on_nth},
{10,"(zero)"},
{2,"L1 Icache policy"},
{4,"Dcache min words/line", two_on_nth},
{4,"Exclusives Reservation Granule", two_on_nth_granule},
{4,"Cache Writeback Granule", two_on_nth_granule},
{1,"(zero)"},
{3,"(register format)"},
{}
}

Definiert in Zeile 156 der Datei cpuinfo_v7.c.

struct cpuinfo_bitfield_desc_s cpuinf_dbgd_address[]
static
Initialisierung:
= {
{2,"Valid"},
{10,"- (UNK)"},
{20,"Address",cache_tcm_addr_str},
{}
}

Definiert in Zeile 384 der Datei cpuinfo_v7.c.

struct cpuinfo_bitfield_desc_s cpuinf_dbgdidr[]
static
Initialisierung:
= {
{4,"Revision"},
{4,"Variant"},
{8,"- (RAZ)"},
{4,"Version",dbg_version},
{4,"Context",ccsidr_plusone},
{4,"BRP",ccsidr_plusone},
{4,"WRP",ccsidr_plusone},
{}
}

Definiert in Zeile 373 der Datei cpuinfo_v7.c.

struct cpuinfo_bitfield_desc_s cpuinf_dbgdscr[]
static
Initialisierung:
= {
{1,"HALTED"},
{1,"RESTARTED"},
{4,"MOE"},
{1,"SDABORT_l"},
{1,"ADABORT_l"},
{1,"UND_l"},
{1,"FS"},
{1,"DBGack"},
{1,"INTdis"},
{1,"UDCCdis"},
{1,"ITRen"},
{1,"HDBGen"},
{1,"MDBGen"},
{1,"SPIDdis"},
{1,"SPNIDdis"},
{1,"NS"},
{1,"ADAdiscard"},
{2,"ExtDCCmode"},
{2,"- (SBZ)"},
{1,"InstrCompl_l"},
{1,"PipeAdv"},
{1,"TXfull_l"},
{1,"RXfull_l"},
{1,"- (SBZ)"},
{1,"TXfull"},
{1,"RXfull"},
{1,"- (SBZ)"},
{}
}

Definiert in Zeile 391 der Datei cpuinfo_v7.c.

struct cpuinfo_bitfield_desc_s cpuinf_feat0[]
Initialisierung:
= {
{4,"ARM inst set"},
{4,"Thumb inst set"},
{4,"Jazelle inst set"},
{4,"ThumbEE inst set"},
{16,"-"},
{}
}

Definiert in Zeile 29 der Datei cpuinfo_v7.c.

struct cpuinfo_bitfield_desc_s cpuinf_feat1[]
Initialisierung:
= {
{4,"Programmers' model"},
{4,"Security extensions"},
{4,"Microcontr. prog model"},
{20,"-"},
{}
}

Definiert in Zeile 38 der Datei cpuinfo_v7.c.

struct cpuinfo_bitfield_desc_s cpuinf_generic[]
Initialisierung:
= {
{32,"(raw value)"},
{}
}

Definiert in Zeile 354 der Datei cpuinfo_v7.c.

struct cpuinfo_bitfield_desc_s cpuinf_isar0[]
Initialisierung:
= {
{4,"Swap instrs"},
{4,"Bitcount instrs"},
{4,"Bitfield instrs"},
{4,"CmpBranch instrs"},
{4,"Coproc instrs"},
{4,"Debug instrs"},
{4,"Divide instrs"},
{4,"-"},
{}
}

Definiert in Zeile 91 der Datei cpuinfo_v7.c.

struct cpuinfo_bitfield_desc_s cpuinf_isar1[]
Initialisierung:
= {
{4,"Endian instrs"},
{4,"Exception instrs"},
{4,"Exception AR instrs"},
{4,"Extend instrs"},
{4,"IfThen instrs"},
{4,"Immediate instrs"},
{4,"Interwork instrs"},
{4,"Jazelle instrs"},
{}
}

Definiert in Zeile 103 der Datei cpuinfo_v7.c.

struct cpuinfo_bitfield_desc_s cpuinf_isar2[]
Initialisierung:
= {
{4,"LoadStore instrs"},
{4,"Memhint instrs"},
{4,"MultiAccess Interruptible instructions"},
{4,"Mult instrs"},
{4,"MultS instrs"},
{4,"MultU instrs"},
{4,"PSR AR instrs"},
{4,"Reversal instrs"},
{}
}

Definiert in Zeile 115 der Datei cpuinfo_v7.c.

struct cpuinfo_bitfield_desc_s cpuinf_isar3[]
Initialisierung:
= {
{4,"Saturate instrs"},
{4,"SIMD instrs"},
{4,"SVC instrs"},
{4,"SynchPrim instrs"},
{4,"TabBranch instrs"},
{4,"ThumbCopy instrs"},
{4,"TrueNOP instrs"},
{4,"T2 Exec Env instrs"},
{}
}

Definiert in Zeile 127 der Datei cpuinfo_v7.c.

struct cpuinfo_bitfield_desc_s cpuinf_isar4[]
Initialisierung:
= {
{4,"Unprivileged instrs"},
{4,"WithShifts instrs"},
{4,"Writeback instrs"},
{4,"SMC instrs"},
{4,"Barrier instrs"},
{4,"SynchPrim_instrs_frac"},
{4,"PSR_M instrs"},
{4,"-"},
{}
}

Definiert in Zeile 139 der Datei cpuinfo_v7.c.

struct cpuinfo_bitfield_desc_s cpuinf_isar5[]
Initialisierung:
= {
{32,"-"},
{}
}

Definiert in Zeile 151 der Datei cpuinfo_v7.c.

struct cpuinfo_bitfield_desc_s cpuinf_mmfr0[]
Initialisierung:
= {
{4,"VMSA support"},
{4,"PMSA support"},
{4,"Cache coherence"},
{4,"Outer shareable"},
{4,"TCM support"},
{4,"Auxiliary registers"},
{4,"FCSE support"},
{4,"-"},
{}
}

Definiert in Zeile 46 der Datei cpuinfo_v7.c.

struct cpuinfo_bitfield_desc_s cpuinf_mmfr1[]
Initialisierung:
= {
{4,"L1 Harvard cache VA"},
{4,"L1 unified cache VA"},
{4,"L1 Harvard cache s/w"},
{4,"L1 unified cache s/w"},
{4,"L1 Harvard cache"},
{4,"L1 unified cache"},
{4,"L1 cache test & clean"},
{4,"Branch predictor"},
{}
}

Definiert in Zeile 58 der Datei cpuinfo_v7.c.

struct cpuinfo_bitfield_desc_s cpuinf_mmfr2[]
Initialisierung:
= {
{4,"L1 Harvard fg prefetch"},
{4,"L1 Harvard bg prefetch"},
{4,"L1 Harvard range"},
{4,"Harvard TLB"},
{4,"Unified TLB"},
{4,"Mem barrier"},
{4,"WFI stall"},
{4,"HW access flag"},
{}
}

Definiert in Zeile 70 der Datei cpuinfo_v7.c.

struct cpuinfo_bitfield_desc_s cpuinf_mmfr3[]
Initialisierung:
= {
{4,"Cache maintain MVA"},
{4,"Cache maintain s/w"},
{4,"BP maintain"},
{16,"-"},
{4,"Supersection support"},
{}
}

Definiert in Zeile 82 der Datei cpuinfo_v7.c.

struct cpuinfo_bitfield_desc_s cpuinf_mpubase[]
Initialisierung:
= {
{32,"Base address"},
{}
}

Definiert in Zeile 250 der Datei cpuinfo_v7.c.

struct cpuinfo_bitfield_desc_s cpuinf_mpusizeen[]
Initialisierung:
= {
{1,"Enabled"},
{5,"Size", mpu_region_size_str},
{2,"-"},
{8,"Sub-regions disabled", bitfield8},
{}
}

Definiert in Zeile 301 der Datei cpuinfo_v7.c.

struct cpuinfo_bitfield_desc_s cpuinf_mputype[]
Initialisierung:
= {
{1,"S"},
{7,"-"},
{8,"Num of MPU regions"},
{}
}

Definiert in Zeile 243 der Datei cpuinfo_v7.c.

struct cpuinfo_bitfield_desc_s cpuinf_sctlr[]
Initialisierung:
= {
{1,"MPU Enable"},
{1,"Strict Align"},
{1,"L1 DCache Enable"},
{4,"- (SBO)"},
{4,"- (SBZ)"},
{1,"Branch Pred Enable"},
{1,"L1 ICache Enable"},
{1,"High Vector"},
{1,"Round Robin"},
{1,"- (SBZ)"},
{1,"- (SBO)"},
{1,"MPU background reg"},
{1,"- (SBO)"},
{1,"Div0 exception"},
{1,"- (SBZ)"},
{1,"FIQ Enable"},
{2,"- (SBO)"},
{1,"VIC"},
{1,"CPSR E bit"},
{1,"- (SBZ)"},
{1,"NMFI"},
{1,"TRE"},
{1,"AFE"},
{1,"Thumb exceptions"},
{1,"Endian"},
{}
}

Definiert in Zeile 255 der Datei cpuinfo_v7.c.

struct cpuinfo_bitfield_desc_s cpuinf_tcmreg[]
Initialisierung:
= {
{1,"Enabled"},
{1,"-"},
{5,"Size", cache_tcm_size_str},
{5,"-"},
{20,"Base address", cache_tcm_addr_str},
{}
}

Definiert in Zeile 234 der Datei cpuinfo_v7.c.

struct cpuinfo_word_desc_s cpuinfo_desc[]

Definiert in Zeile 422 der Datei cpuinfo_v7.c.

char linebuf[128]
static

Definiert in Zeile 3 der Datei cpuinfo_v7.c.

const char* two_nth_str[]
static
Initialisierung:
= {
"1", "2", "4", "8", "16", "32", "64", "128", "256", "512", "1K", "2K", "4K", "8K", "16K", "32K"
}

Definiert in Zeile 5 der Datei cpuinfo_v7.c.