root/loader/ixus140_elph130/main.c

DEFINITIONS

1. my_restart

   1 #include "../generic/check_compat.c"
   3 extern long *blob_chdk_core;
   4 extern long blob_chdk_core_size;
   6 #define DEBUG_LED ((volatile int *)0xC0223030) // AF, green not found
   7 #define DELAY 500000
   9 void __attribute__((noreturn)) my_restart() 
  10 {
  11     // DEBUG: blink led
  12     /*
  13     int counter;
  14 
  15     while(1) {
  16     counter = DELAY; *DEBUG_LED = 0x46;  while (counter--) { asm("nop\n nop\n"); };
  17     counter = DELAY; *DEBUG_LED = 0x44;  while (counter--) { asm("nop\n nop\n"); };
  18     }
  19     */
  21     long *dst = (long*)MEMISOSTART;
  22     const long *src = blob_chdk_core;
  23     long length = (blob_chdk_core_size + 3) >> 2;
core_copy(src, dst, length);
  27 // restart function
  28         // from sub_FF038240 via 0x12345678
  29     // note, the normal stores to a bunch of MMIOs do not appear to be present
  30   asm volatile (
  31         "MRS     R0, CPSR\n"
  32         "BIC     R0, R0, #0x3F\n"
  33         "ORR     R0, R0, #0xD3\n"
  34         "MSR     CPSR, R0\n"
  36         "MOV     R0, #0x78\n"
  37         "MCR     p15, 0, R0,c1,c0\n" // disable caches and TCM
  38         "MOV     R0, #0\n"
  39         "MCR     p15, 0, R0,c7,c10, 4\n" // drain write buffer
  40         "MCR     p15, 0, R0,c7,c5\n" // flush instruction cache
  41         "MCR     p15, 0, R0,c7,c6\n" // flushd data cache
  42         "MOV     R0, #0x80000006\n"
  43         "MCR     p15, 0, R0,c9,c1\n" // set data TCM at 0x80000000, 4kb
  44         "MCR     p15, 0, R0,c9,c1, 1\n" // instruction TCM (DDIO201D says should only write zero as base ...)
  45         "MRC     p15, 0, R0,c1,c0\n" // read control state
  46         "ORR     R0, R0, #0x50000\n" // enable both TCM
  47         "MCR     p15, 0, R0,c1,c0\n"
  48         "LDR     R0, =0x12345678\n"  // marker value stored in TCM
  49         "MOV     R1, #0x80000000\n"
  50         "STR     R0, [R1,#0xFFC]\n"
  51 //      "LDR     R0, =loc_FF000000\n"
  52         "mov     R0, %0\n"
  53 //      "LDMFD   SP!, {R4,LR}\n"
  54         "BX      R0\n"
  55         : : "r"(MEMISOSTART) : "memory","r0","r1","r2","r3","r4");
  57   while(1);
  58 }