1 #include "../generic/check_compat.c"
2
3 // static void __attribute__((noreturn)) shutdown();
4 // static void __attribute__((noreturn)) panic(int cnt);
5
6 extern long *blob_chdk_core;
7 // extern long *blob_copy_and_reset;
8 extern long blob_chdk_core_size;
9 // extern long blob_copy_and_reset_size;
10
11
12
13 void __attribute__((noreturn)) my_restart()
14 {
15 {
16 // char *dst = dst_void;
17 // const char *src = src_void;
18 long *dst = (long*)MEMISOSTART;
19 const long *src = blob_chdk_core;
20 long length = (blob_chdk_core_size + 3) >> 2;
21
22 core_copy(src, dst, length);
23
24 }
25
26 /*
27 * The following asm volatile is used to:
28 * - Change the processor mode to supervisor mode and disable interrupts
29 * - Write all 1s from ___ base over offsets 0x00C to 0x10C
30 * - Do some stuff with co-processor 15 (system control coprocessor)
31 * - Some more stuff
32 * - Adjust the SP, LR and PC. PC points to passed argument dst_void,
33 * which is a pointer to a character. (Currently MEMISOSTART, see end of func)
34 */
35 asm volatile(
36 "MRS R1, CPSR\n" // Save 'current processor status registers' to R1
37 "BIC R1, R1, #0x3F\n" // Change CPSR register to use ARM instruction set and ...
38 "ORR R1, R1, #0xD3\n" // disable interrupts (fast and normal) and set supervisor mode (10011).
39 "MSR CPSR_cf, R1\n" // Write new CPSR back into CPSR reg
40
41 "LDR R2, =0xC0200000\n" // Load register with word from memory - this is used as an address base. Where is this?
42 "MOV R1, #0xFFFFFFFF\n" // Load all 1s into R1 for memory writes that follow.
43 "STR R1, [R2,#0x10C]\n" // This entire block of store commands writes all 1s from base address stored in R2
44 "STR R1, [R2,#0xC]\n" // over the offsets 0x00C to 0x10C.
45 "STR R1, [R2,#0x1C]\n"
46 "STR R1, [R2,#0x2C]\n"
47 "STR R1, [R2,#0x3C]\n"
48 "STR R1, [R2,#0x4C]\n"
49 "STR R1, [R2,#0x5C]\n"
50 "STR R1, [R2,#0x6C]\n"
51 "STR R1, [R2,#0x7C]\n"
52 "STR R1, [R2,#0x8C]\n"
53 "STR R1, [R2,#0x9C]\n"
54 "STR R1, [R2,#0xAC]\n"
55 "STR R1, [R2,#0xBC]\n"
56 "STR R1, [R2,#0xCC]\n"
57 "STR R1, [R2,#0xDC]\n"
58 "STR R1, [R2,#0xEC]\n"
59 "STR R1, [R2,#0xFC]\n" // Done setting all 1s to memory block described above
60
61 /*
62 * The following code makes use of co-processor 15 (system control coprocessor)
63 * CP15 c2-c6, c8, c10, c13 are allocated to memory protection system.
64 * CP15 c7, c9 are allocated to the control of caches and write buffers.
65 * CP15 c11 is allocated to level 1 memory DMA support.
66 * CP15 c12, c14 are reserved.
67 */
68 // Register 1 is for cache and write buffer control bits
69 "MOV R1, #0x78\n" // 0111 1000
70 "MCR p15, 0, R1,c1,c0\n" // disable cache, enable write buffer, disable instruction cache
71 "MOV R1, #0\n"
72 // Register 7 writes are cache management functions
73 "MCR p15, 0, R1,c7,c10, 4\n" // c10, 4 is data sync barrier (used to be drain write buffer) a memory barrier (blocks memory access?)
74 // that completes when: memory access before this instruction are done, all cache ,branch predictor and
75 // translation lookaside buffer (TLB) maintenance operations preceding this instruction are done.
76 "MCR p15, 0, R1,c7,c5\n" // c5, 0 invalidates entire instruction cache
77 "MCR p15, 0, R1,c7,c6\n" // c6, 0 invalidates entire data cache
78 // Register 9 is responsible for cache lockdown functions
79 "MOV R2, #0x40000000\n"
80 "ORR R1, R2, #6\n"
81 "MCR p15, 0, R1,c9,c1\n"
82 "ORR R1, R1, #6\n"
83 "MCR p15, 0, R1,c9,c1, 1\n"
84 // see above for register 1 functions
85 "MRC p15, 0, R1,c1,c0\n" // following lines of code set bits 16 and 18
86 "ORR R1, R1, #0x50000\n"
87 "MCR p15, 0, R1,c1,c0\n"
88
89 "MOV R3, #0xFF0\n"
90 "LDR R1, =0x12345678\n"
91 "ADD R3, R3, #0x4000000C\n"
92 "STR R1, [R3]\n"
93
94 "MOV SP, #0x1900\n"
95 "MOV LR, PC\n"
96 "MOV PC, %0\n"
97 : : "r"(MEMISOSTART) : "memory","r1","r2","r3");
98
99 while(1);
100 }
101
102 // #define LED_PR 0xc0220084
103 //
104 // static void __attribute__((noreturn)) shutdown()
105 // {
106 // volatile long *p = (void*)0xc02200a0;
107 //
108 // asm(
109 // "MRS R1, CPSR\n"
110 // "AND R0, R1, #0x80\n"
111 // "ORR R1, R1, #0x80\n"
112 // "MSR CPSR_cf, R1\n"
113 // :::"r1","r0");
114 //
115 // *p = 0x44;
116 //
117 // while(1);
118 // }
119 //
120 //
121 // static void __attribute__((noreturn)) panic(int cnt)
122 // {
123 // volatile long *p=(void*)LED_PR;
124 // int i;
125 //
126 // for(;cnt>0;cnt--){
127 // p[0]=0x46;
128 //
129 // for(i=0;i<0x200000;i++){
130 // asm ("nop\n");
131 // asm ("nop\n");
132 // }
133 // p[0]=0x44;
134 // for(i=0;i<0x200000;i++){
135 // asm ("nop\n");
136 // asm ("nop\n");
137 // }
138 // }
139 // shutdown();
140 // }