root/loader/n/main.c

DEFINITIONS

1. my_restart

   1 #include "../generic/check_compat.c"
   3 extern long *blob_chdk_core;
   4 extern long blob_chdk_core_size;
   7 void __attribute__((noreturn)) my_restart() 
   8 {
  10     long *dst = (long*)MEMISOSTART;
  11     const long *src = blob_chdk_core;
  12     long length = (blob_chdk_core_size + 3) >> 2;
core_copy(src, dst, length);
  16 // restart function
  17         // from sub_ff0395d4 via 0x12345678
  19 // 
  22   asm volatile (
  23         "MRS     R0, CPSR\n"
  24         "BIC     R0, R0, #0x3F\n"
  25         "ORR     R0, R0, #0xD3\n"
  26         "MSR     CPSR, R0\n"
  28         "MOV     R0, #0x78\n"           //****  <-  0xff0395d4
  29         "MCR     p15, 0, R0,c1,c0\n" // disable caches and TCM
  30         "MOV     R0, #0\n"
  31         "MCR     p15, 0, R0,c7,c10, 4\n" // drain write buffer
  32         "MCR     p15, 0, R0,c7,c5\n" // flush instruction cache
  33         "MCR     p15, 0, R0,c7,c6\n" // flushd data cache
  34         "MOV     R0, #0x80000006\n"
  35         "MCR     p15, 0, R0,c9,c1\n" // set data TCM at 0x80000000, 4kb
  36         "MCR     p15, 0, R0,c9,c1, 1\n" // instruction TCM (DDIO201D says should only write zero as base ...)
  37         "MRC     p15, 0, R0,c1,c0\n" // read control state
  38         "ORR     R0, R0, #0x50000\n" // enable both TCM
  39         "MCR     p15, 0, R0,c1,c0\n"
  40         "LDR     R0, =0x12345678\n"  // marker value stored in TCM
  41         "MOV     R1, #0x80000000\n"
  42         "STR     R0, [R1,#0xFFC]\n"    //***** <- 0xff03960c
  44         "mov     R0, %0\n"         // change jump address (was 0xFF000000)
  45         "BX      R0\n"             //**** <- 0xff039618
  47         : : "r"(MEMISOSTART) : "memory","r0","r1","r2","r3","r4");
  49    while(1);
  50 }