This source file includes following definitions.
- taskHook
- CreateTask_spytask
- boot
- sub_FFC001A4_my
- sub_FFC00F98_my
- uHwSetup_my
- taskcreate_Startup_my
- task_Startup_my
- taskcreatePhySw_my
- init_file_modules_task
- sub_FFC59D98_my
- sub_FFC3FC50_my
- sub_FFC3FA8C_my
- sub_FFC3F81C_my
1
2
3
4 #include "lolevel.h"
5 #include "platform.h"
6 #include "core.h"
7 #include "dryos31.h"
8
9 #define offsetof(TYPE, MEMBER) ((int) &((TYPE *)0)->MEMBER)
10
11 const char * const new_sa = &_end;
12
13 extern void task_CaptSeq();
14 extern void task_InitFileModules();
15 extern void task_MovieRecord();
16 extern void task_ExpDrv();
17 extern void task_FileWrite();
18
19 void taskHook(context_t **context)
20 {
21 task_t *tcb=(task_t*)((char*)context-offsetof(task_t, context));
22
23
24 if(tcb->entry == (void*)task_CaptSeq) tcb->entry = (void*)capt_seq_task;
25 if(tcb->entry == (void*)task_InitFileModules) tcb->entry = (void*)init_file_modules_task;
26 if(tcb->entry == (void*)task_MovieRecord) tcb->entry = (void*)movie_record_task;
27 if(tcb->entry == (void*)task_ExpDrv) tcb->entry = (void*)exp_drv_task;
28 if(tcb->entry == (void*)task_FileWrite) tcb->entry = (void*)filewritetask;
29 }
30
31
32
33
34 void CreateTask_spytask() {
35 _CreateTask("SpyTask", 0x19, 0x2000, core_spytask, 0);
36 };
37
38
39
40
41
42
43
44
45
46 void __attribute__((naked,noinline)) boot() {
47 asm volatile (
48 " LDR R1, =0xC0410000 \n"
49 " MOV R0, #0 \n"
50 " STR R0, [R1] \n"
51 " MOV R1, #0x78 \n"
52 " MCR p15, 0, R1, c1, c0 \n"
53 " MOV R1, #0 \n"
54 " MCR p15, 0, R1, c7, c10, 4 \n"
55 " MCR p15, 0, R1, c7, c5 \n"
56 " MCR p15, 0, R1, c7, c6 \n"
57 " MOV R0, #0x3D \n"
58 " MCR p15, 0, R0, c6, c0 \n"
59 " MOV R0, #0xC000002F \n"
60 " MCR p15, 0, R0, c6, c1 \n"
61 " MOV R0, #0x33 \n"
62 " MCR p15, 0, R0, c6, c2 \n"
63 " LDR R0, =0x10000033 \n"
64 " MCR p15, 0, R0, c6, c3 \n"
65 " MOV R0, #0x40000017 \n"
66 " MCR p15, 0, R0, c6, c4 \n"
67 " LDR R0, =0xFFC0002B \n"
68 " MCR p15, 0, R0, c6, c5 \n"
69 " MOV R0, #0x34 \n"
70 " MCR p15, 0, R0, c2, c0 \n"
71 " MOV R0, #0x34 \n"
72 " MCR p15, 0, R0, c2, c0, 1 \n"
73 " MOV R0, #0x34 \n"
74 " MCR p15, 0, R0, c3, c0 \n"
75 " LDR R0, =0x3333330 \n"
76 " MCR p15, 0, R0, c5, c0, 2 \n"
77 " LDR R0, =0x3333330 \n"
78 " MCR p15, 0, R0, c5, c0, 3 \n"
79 " MRC p15, 0, R0, c1, c0 \n"
80 " ORR R0, R0, #0x1000 \n"
81 " ORR R0, R0, #4 \n"
82 " ORR R0, R0, #1 \n"
83 " MCR p15, 0, R0, c1, c0 \n"
84 " MOV R1, #0x40000006 \n"
85 " MCR p15, 0, R1, c9, c1 \n"
86 " MOV R1, #6 \n"
87 " MCR p15, 0, R1, c9, c1, 1 \n"
88 " MRC p15, 0, R1, c1, c0 \n"
89 " ORR R1, R1, #0x50000 \n"
90 " MCR p15, 0, R1, c1, c0 \n"
91 " LDR R2, =0xC0200000 \n"
92 " MOV R1, #1 \n"
93 " STR R1, [R2, #0x10C] \n"
94 " MOV R1, #0xFF \n"
95 " STR R1, [R2, #0xC] \n"
96 " STR R1, [R2, #0x1C] \n"
97 " STR R1, [R2, #0x2C] \n"
98 " STR R1, [R2, #0x3C] \n"
99 " STR R1, [R2, #0x4C] \n"
100 " STR R1, [R2, #0x5C] \n"
101 " STR R1, [R2, #0x6C] \n"
102 " STR R1, [R2, #0x7C] \n"
103 " STR R1, [R2, #0x8C] \n"
104 " STR R1, [R2, #0x9C] \n"
105 " STR R1, [R2, #0xAC] \n"
106 " STR R1, [R2, #0xBC] \n"
107 " STR R1, [R2, #0xCC] \n"
108 " STR R1, [R2, #0xDC] \n"
109 " STR R1, [R2, #0xEC] \n"
110 " STR R1, [R2, #0xFC] \n"
111 " LDR R1, =0xC0400008 \n"
112 " LDR R2, =0x430005 \n"
113 " STR R2, [R1] \n"
114 " MOV R1, #1 \n"
115 " LDR R2, =0xC0243100 \n"
116 " STR R2, [R1] \n"
117 " LDR R2, =0xC0242010 \n"
118 " LDR R1, [R2] \n"
119 " ORR R1, R1, #1 \n"
120 " STR R1, [R2] \n"
121 " LDR R0, =0xFFEEAE90 \n"
122 " LDR R1, =0x1900 \n"
123 " LDR R3, =0xDF7C \n"
124
125 "loc_FFC0013C:\n"
126 " CMP R1, R3 \n"
127 " LDRCC R2, [R0], #4 \n"
128 " STRCC R2, [R1], #4 \n"
129 " BCC loc_FFC0013C \n"
130 " LDR R1, =0xD4EC8 \n"
131 " MOV R2, #0 \n"
132
133 "loc_FFC00154:\n"
134 " CMP R3, R1 \n"
135 " STRCC R2, [R3], #4 \n"
136 " BCC loc_FFC00154 \n"
137 " B sub_FFC001A4_my \n"
138 );
139 }
140
141
142
143 void __attribute__((naked,noinline)) sub_FFC001A4_my() {
144
145
146 *(int*)0x1930=(int)taskHook;
147 *(int*)0x1934=(int)taskHook;
148
149
150
151 *(int*)(0x22A0+0x4)= (*(int*)0xC02200B8) & 1 ? 0x200000 : 0x100000;
152
153 asm volatile (
154 " LDR R0, =0xFFC0021C \n"
155 " MOV R1, #0 \n"
156 " LDR R3, =0xFFC00254 \n"
157
158 "loc_FFC001B0:\n"
159 " CMP R0, R3 \n"
160 " LDRCC R2, [R0], #4 \n"
161 " STRCC R2, [R1], #4 \n"
162 " BCC loc_FFC001B0 \n"
163 " LDR R0, =0xFFC00254 \n"
164 " MOV R1, #0x4B0 \n"
165 " LDR R3, =0xFFC00468 \n"
166
167 "loc_FFC001CC:\n"
168 " CMP R0, R3 \n"
169 " LDRCC R2, [R0], #4 \n"
170 " STRCC R2, [R1], #4 \n"
171 " BCC loc_FFC001CC \n"
172 " MOV R0, #0xD2 \n"
173 " MSR CPSR_cxsf, R0 \n"
174 " MOV SP, #0x1000 \n"
175 " MOV R0, #0xD3 \n"
176 " MSR CPSR_cxsf, R0 \n"
177 " MOV SP, #0x1000 \n"
178 " LDR R0, =0x6C4 \n"
179 " LDR R2, =0xEEEEEEEE \n"
180 " MOV R3, #0x1000 \n"
181
182 "loc_FFC00200:\n"
183 " CMP R0, R3 \n"
184 " STRCC R2, [R0], #4 \n"
185 " BCC loc_FFC00200 \n"
186 " BL sub_FFC00F98_my \n"
187 );
188 }
189
190
191
192 void __attribute__((naked,noinline)) sub_FFC00F98_my() {
193 asm volatile (
194 " STR LR, [SP, #-4]! \n"
195 " SUB SP, SP, #0x74 \n"
196 " MOV R0, SP \n"
197 " MOV R1, #0x74 \n"
198 " BL sub_FFE71838 \n"
199 " MOV R0, #0x53000 \n"
200 " STR R0, [SP, #4] \n"
201
202 #if defined(CHDK_NOT_IN_CANON_HEAP)
203 " LDR R0, =0xD4EC8 \n"
204 #else
205 " LDR R0, =new_sa\n"
206 " LDR R0, [R0]\n"
207 #endif
208
209 " LDR R2, =0x279C00 \n"
210 " LDR R1, =0x2724A8 \n"
211 " STR R0, [SP, #8] \n"
212 " SUB R0, R1, R0 \n"
213 " ADD R3, SP, #0xC \n"
214 " STR R2, [SP] \n"
215 " STMIA R3, {R0-R2} \n"
216 " MOV R0, #0x22 \n"
217 " STR R0, [SP, #0x18] \n"
218 " MOV R0, #0x68 \n"
219 " STR R0, [SP, #0x1C] \n"
220 " LDR R0, =0x19B \n"
221 " LDR R1, =uHwSetup_my \n"
222 " STR R0, [SP, #0x20] \n"
223 " MOV R0, #0x96 \n"
224 " STR R0, [SP, #0x24] \n"
225 " MOV R0, #0x78 \n"
226 " STR R0, [SP, #0x28] \n"
227 " MOV R0, #0x64 \n"
228 " STR R0, [SP, #0x2C] \n"
229 " MOV R0, #0 \n"
230 " STR R0, [SP, #0x30] \n"
231 " STR R0, [SP, #0x34] \n"
232 " MOV R0, #0x10 \n"
233 " STR R0, [SP, #0x5C] \n"
234 " MOV R0, #0x800 \n"
235 " STR R0, [SP, #0x60] \n"
236 " MOV R0, #0xA0 \n"
237 " STR R0, [SP, #0x64] \n"
238 " MOV R0, #0x280 \n"
239 " STR R0, [SP, #0x68] \n"
240 " MOV R0, SP \n"
241 " MOV R2, #0 \n"
242 " BL sub_FFC02D3C \n"
243 " ADD SP, SP, #0x74 \n"
244 " LDR PC, [SP], #4 \n"
245 );
246 }
247
248
249
250 void __attribute__((naked,noinline)) uHwSetup_my() {
251 asm volatile (
252 " STMFD SP!, {R4,LR} \n"
253 " BL sub_FFC00944 \n"
254 " BL sub_FFC09708 \n"
255 " CMP R0, #0 \n"
256 " LDRLT R0, =0xFFC04EA4 /*'dmSetup'*/ \n"
257 " BLLT _err_init_task \n"
258 " BL sub_FFC049B8 \n"
259 " CMP R0, #0 \n"
260 " LDRLT R0, =0xFFC04EAC /*'termDriverInit'*/ \n"
261 " BLLT _err_init_task \n"
262 " LDR R0, =0xFFC04EBC /*'/_term'*/ \n"
263 " BL sub_FFC04AA0 \n"
264 " CMP R0, #0 \n"
265 " LDRLT R0, =0xFFC04EC4 /*'termDeviceCreate'*/ \n"
266 " BLLT _err_init_task \n"
267 " LDR R0, =0xFFC04EBC /*'/_term'*/ \n"
268 " BL sub_FFC0354C \n"
269 " CMP R0, #0 \n"
270 " LDRLT R0, =0xFFC04ED8 /*'stdioSetup'*/ \n"
271 " BLLT _err_init_task \n"
272 " BL sub_FFC09290 \n"
273 " CMP R0, #0 \n"
274 " LDRLT R0, =0xFFC04EE4 /*'stdlibSetup'*/ \n"
275 " BLLT _err_init_task \n"
276 " BL sub_FFC0147C \n"
277 " CMP R0, #0 \n"
278 " LDRLT R0, =0xFFC04EF0 /*'armlib_setup'*/ \n"
279 " BLLT _err_init_task \n"
280 " LDMFD SP!, {R4,LR} \n"
281 " B taskcreate_Startup_my \n"
282 );
283 }
284
285
286
287 void __attribute__((naked,noinline)) taskcreate_Startup_my() {
288 asm volatile (
289 " STMFD SP!, {R3,LR} \n"
290
291 " BL sub_FFC18AE0 \n"
292 " CMP R0, #0 \n"
293 " BNE loc_FFC0CDA0 \n"
294 " BL sub_FFC30FFC \n"
295 " CMP R0, #0 \n"
296 " BNE loc_FFC0CDA0 \n"
297 " LDR R1, =0xC0220000 \n"
298 " MOV R0, #0x44 \n"
299 " STR R0, [R1, #0xA4] \n"
300 " STR R0, [R1, #0xA0] \n"
301
302 "loc_FFC0CD9C:\n"
303 " B loc_FFC0CD9C \n"
304
305 "loc_FFC0CDA0:\n"
306
307
308 " BL sub_FFC16E70 \n"
309 " LDR R1, =0x2CE000 \n"
310 " MOV R0, #0 \n"
311 " BL sub_FFC170B8 \n"
312 " BL sub_FFC17064 /*_EnableDispatch*/ \n"
313 " MOV R3, #0 \n"
314 " STR R3, [SP] \n"
315 " LDR R3, =task_Startup_my \n"
316 " MOV R2, #0 \n"
317 " MOV R1, #0x19 \n"
318 " LDR R0, =0xFFC0CDE8 /*'Startup'*/ \n"
319 " BL _CreateTask \n"
320 " MOV R0, #0 \n"
321 " LDMFD SP!, {R12,PC} \n"
322 );
323 }
324
325
326
327 void __attribute__((naked,noinline)) task_Startup_my() {
328 asm volatile (
329 " STMFD SP!, {R4,LR} \n"
330 " BL sub_FFC0515C \n"
331 " BL sub_FFC12304 \n"
332 " BL sub_FFC10BE0 \n"
333
334 " BL sub_FFC18CE8 \n"
335
336 " BL sub_FFC5D000 \n"
337 " BL sub_FFC18D38 \n"
338 " BL sub_FFC16164 \n"
339 " BL sub_FFC18EA4 \n"
340 " BL CreateTask_spytask\n"
341 " BL taskcreatePhySw_my \n"
342 " BL sub_FFC141EC \n"
343 " BL sub_FFC18EBC \n"
344
345 " BL sub_FFC10530 \n"
346 " BL sub_FFC188C0 \n"
347 " BL sub_FFC10B90 \n"
348 " BL sub_FFC1044C \n"
349 " BL sub_FFC19944 \n"
350 " BL sub_FFC10424 \n"
351 " LDMFD SP!, {R4,LR} \n"
352 );
353 }
354
355
356
357 void __attribute__((naked,noinline)) taskcreatePhySw_my() {
358 asm volatile (
359 " STMFD SP!, {R3-R5,LR} \n"
360 " LDR R4, =0x1BD8 \n"
361 " LDR R0, [R4, #0x10] \n"
362 " CMP R0, #0 \n"
363 " BNE sub_FFC110C8 \n"
364 " MOV R3, #0 \n"
365 " STR R3, [SP] \n"
366 " LDR R3, =mykbd_task \n"
367 " MOV R2, #0x2000 \n"
368 " LDR PC, =0xFFC110B8 \n"
369 );
370 }
371
372
373
374 void __attribute__((naked,noinline)) init_file_modules_task() {
375 asm volatile (
376 " STMFD SP!, {R4-R6,LR} \n"
377 " BL sub_FFC59D6C \n"
378 " LDR R5, =0x5006 \n"
379 " MOVS R4, R0 \n"
380 " MOVNE R1, #0 \n"
381 " MOVNE R0, R5 \n"
382 " BLNE _PostLogicalEventToUI \n"
383 " BL sub_FFC59D98_my \n"
384 " BL core_spytask_can_start\n"
385 " CMP R4, #0 \n"
386 " MOVEQ R0, R5 \n"
387 " LDMEQFD SP!, {R4-R6,LR} \n"
388 " MOVEQ R1, #0 \n"
389 " BEQ _PostLogicalEventToUI \n"
390 " LDMFD SP!, {R4-R6,PC} \n"
391 );
392 }
393
394
395
396 void __attribute__((naked,noinline)) sub_FFC59D98_my() {
397 asm volatile (
398 " STMFD SP!, {R4,LR} \n"
399 " BL sub_FFC3FC50_my \n"
400 " LDR PC, =0xFFC59DA0 \n"
401 );
402 }
403
404
405
406 void __attribute__((naked,noinline)) sub_FFC3FC50_my() {
407 asm volatile (
408 " STMFD SP!, {R4-R6,LR} \n"
409 " MOV R6, #0 \n"
410 " MOV R0, R6 \n"
411 " BL sub_FFC3F710 \n"
412 " LDR R4, =0x176A4 \n"
413 " MOV R5, #0 \n"
414 " LDR R0, [R4, #0x38] \n"
415 " BL sub_FFC40170 \n"
416 " CMP R0, #0 \n"
417 " LDREQ R0, =0x26F8 \n"
418 " STREQ R5, [R0, #0x10] \n"
419 " STREQ R5, [R0, #0x14] \n"
420 " STREQ R5, [R0, #0x18] \n"
421 " MOV R0, R6 \n"
422 " BL sub_FFC3F750 \n"
423 " MOV R0, R6 \n"
424 " BL sub_FFC3FA8C_my \n"
425 " MOV R5, R0 \n"
426 " MOV R0, R6 \n"
427 " BL sub_FFC3FAF8 \n"
428 " LDR R1, [R4, #0x3C] \n"
429 " AND R2, R5, R0 \n"
430 " CMP R1, #0 \n"
431 " MOV R0, #0 \n"
432 " MOVEQ R0, #0x80000001 \n"
433 " BEQ loc_FFC3FCE4 \n"
434 " LDR R3, [R4, #0x2C] \n"
435 " CMP R3, #2 \n"
436 " MOVEQ R0, #4 \n"
437 " CMP R1, #5 \n"
438 " ORRNE R0, R0, #1 \n"
439 " BICEQ R0, R0, #1 \n"
440 " CMP R2, #0 \n"
441 " BICEQ R0, R0, #2 \n"
442 " ORREQ R0, R0, #0x80000000 \n"
443 " BICNE R0, R0, #0x80000000 \n"
444 " ORRNE R0, R0, #2 \n"
445
446 "loc_FFC3FCE4:\n"
447 " STR R0, [R4, #0x40] \n"
448 " LDMFD SP!, {R4-R6,PC} \n"
449 );
450 }
451
452
453
454 void __attribute__((naked,noinline)) sub_FFC3FA8C_my() {
455 asm volatile (
456 " STMFD SP!, {R4-R6,LR} \n"
457 " LDR R5, =0x26F8 \n"
458 " MOV R6, R0 \n"
459 " LDR R0, [R5, #0x14] \n"
460 " CMP R0, #0 \n"
461 " MOVNE R0, #1 \n"
462 " LDMNEFD SP!, {R4-R6,PC} \n"
463 " MOV R0, #0x17 \n"
464 " MUL R1, R0, R6 \n"
465 " LDR R0, =0x176A4 \n"
466 " ADD R4, R0, R1, LSL#2 \n"
467 " LDR R0, [R4, #0x38] \n"
468 " MOV R1, R6 \n"
469 " BL sub_FFC3F81C_my \n"
470 " CMP R0, #0 \n"
471 " LDMEQFD SP!, {R4-R6,PC} \n"
472 " LDR R0, [R4, #0x38] \n"
473 " MOV R1, R6 \n"
474 " BL sub_FFC3F984 \n"
475 " CMP R0, #0 \n"
476 " LDMEQFD SP!, {R4-R6,PC} \n"
477 " MOV R0, R6 \n"
478 " BL sub_FFC3F318 \n"
479 " CMP R0, #0 \n"
480 " MOVNE R1, #1 \n"
481 " STRNE R1, [R5, #0x14] \n"
482 " LDMFD SP!, {R4-R6,PC} \n"
483 );
484 }
485
486
487
488 void __attribute__((naked,noinline)) sub_FFC3F81C_my() {
489 asm volatile (
490 " STMFD SP!, {R4-R8,LR} \n"
491 " MOV R8, R0 \n"
492 " MOV R0, #0x17 \n"
493 " MUL R1, R0, R1 \n"
494 " LDR R0, =0x176A4 \n"
495 " MOV R6, #0 \n"
496 " ADD R7, R0, R1, LSL#2 \n"
497 " LDR R0, [R7, #0x3C] \n"
498 " MOV R5, #0 \n"
499 " CMP R0, #6 \n"
500 " ADDLS PC, PC, R0, LSL#2 \n"
501 " B loc_FFC3F968 \n"
502 " B loc_FFC3F880 \n"
503 " B loc_FFC3F868 \n"
504 " B loc_FFC3F868 \n"
505 " B loc_FFC3F868 \n"
506 " B loc_FFC3F868 \n"
507 " B loc_FFC3F960 \n"
508 " B loc_FFC3F868 \n"
509
510 "loc_FFC3F868:\n"
511 " MOV R2, #0 \n"
512 " MOV R1, #0x200 \n"
513 " MOV R0, #2 \n"
514 " BL _exmem_ualloc \n"
515 " MOVS R4, R0 \n"
516 " BNE loc_FFC3F888 \n"
517
518 "loc_FFC3F880:\n"
519 " MOV R0, #0 \n"
520 " LDMFD SP!, {R4-R8,PC} \n"
521
522 "loc_FFC3F888:\n"
523 " LDR R12, [R7, #0x4C] \n"
524 " MOV R3, R4 \n"
525 " MOV R2, #1 \n"
526 " MOV R1, #0 \n"
527 " MOV R0, R8 \n"
528 " BLX R12 \n"
529 " CMP R0, #1 \n"
530 " BNE loc_FFC3F8B4 \n"
531 " MOV R0, #2 \n"
532 " BL _exmem_ufree \n"
533 " B loc_FFC3F880 \n"
534
535 "loc_FFC3F8B4:\n"
536 " MOV R0, R8 \n"
537 " BL sub_FFCF51D4 \n"
538
539 " MOV R1, R4\n"
540 " BL mbr_read_dryos\n"
541
542
543
544
545
546
547 " MOV R12, R4\n"
548 " MOV LR, R4\n"
549 " MOV R1, #1\n"
550 " B dg_sd_fat32_enter\n"
551 "dg_sd_fat32:\n"
552 " CMP R1, #4\n"
553 " BEQ dg_sd_fat32_end\n"
554 " ADD R12, R12, #0x10\n"
555 " ADD R1, R1, #1\n"
556 "dg_sd_fat32_enter:\n"
557 " LDRB R2, [R12, #0x1BE]\n"
558 " LDRB R3, [R12, #0x1C2]\n"
559 " CMP R3, #0xB\n"
560 " CMPNE R3, #0xC\n"
561 " CMPNE R3, #0x7\n"
562 " BNE dg_sd_fat32\n"
563 " CMP R2, #0x00\n"
564 " CMPNE R2, #0x80\n"
565 " BNE dg_sd_fat32\n"
566
567 " MOV R4, R12\n"
568
569 "dg_sd_fat32_end:\n"
570
571
572 " LDRB R1, [R4, #0x1C9] \n"
573 " LDRB R3, [R4, #0x1C8] \n"
574 " LDRB R12, [R4, #0x1CC] \n"
575 " MOV R1, R1, LSL#24 \n"
576 " ORR R1, R1, R3, LSL#16 \n"
577 " LDRB R3, [R4, #0x1C7] \n"
578 " LDRB R2, [R4, #0x1BE] \n"
579
580 " ORR R1, R1, R3, LSL#8 \n"
581 " LDRB R3, [R4, #0x1C6] \n"
582 " CMP R2, #0 \n"
583 " CMPNE R2, #0x80 \n"
584 " ORR R1, R1, R3 \n"
585 " LDRB R3, [R4, #0x1CD] \n"
586 " MOV R3, R3, LSL#24 \n"
587 " ORR R3, R3, R12, LSL#16 \n"
588 " LDRB R12, [R4, #0x1CB] \n"
589 " ORR R3, R3, R12, LSL#8 \n"
590 " LDRB R12, [R4, #0x1CA] \n"
591 " ORR R3, R3, R12 \n"
592
593
594 " LDRB R12, [LR,#0x1FE]\n"
595 " LDRB LR, [LR,#0x1FF]\n"
596
597 " MOV R4, #0 \n"
598 " BNE loc_FFC3F93C \n"
599 " CMP R0, R1 \n"
600 " BCC loc_FFC3F93C \n"
601 " ADD R2, R1, R3 \n"
602 " CMP R2, R0 \n"
603 " CMPLS R12, #0x55 \n"
604 " CMPEQ LR, #0xAA \n"
605 " MOVEQ R6, R1 \n"
606 " MOVEQ R5, R3 \n"
607 " MOVEQ R4, #1 \n"
608
609 "loc_FFC3F93C:\n"
610 " MOV R0, #2 \n"
611 " BL _exmem_ufree \n"
612 " CMP R4, #0 \n"
613 " BNE loc_FFC3F974 \n"
614 " MOV R6, #0 \n"
615 " MOV R0, R8 \n"
616 " BL sub_FFCF51D4 \n"
617 " MOV R5, R0 \n"
618 " B loc_FFC3F974 \n"
619
620 "loc_FFC3F960:\n"
621 " MOV R5, #0x40 \n"
622 " B loc_FFC3F974 \n"
623
624 "loc_FFC3F968:\n"
625 " LDR R1, =0x37A \n"
626 " LDR R0, =0xFFC3F810 /*'Mounter.c'*/ \n"
627 " BL _DebugAssert \n"
628
629 "loc_FFC3F974:\n"
630 " STR R6, [R7, #0x44]! \n"
631 " MOV R0, #1 \n"
632 " STR R5, [R7, #4] \n"
633 " LDMFD SP!, {R4-R8,PC} \n"
634 );
635 }