This source file includes following definitions.
- capt_seq_task
- sub_FFC4B554_my
- sub_FFD0C284_my
- exp_drv_task
- sub_FFC81D40_my
- sub_FFC6E480_my
1
2
3
4 #include "lolevel.h"
5 #include "platform.h"
6 #include "core.h"
7
8 #define USE_STUBS_NRFLAG 1
9
10 #include "../../../generic/capt_seq.c"
11
12
13
14 void __attribute__((naked,noinline)) capt_seq_task() {
15 asm volatile (
16 " STMFD SP!, {R3-R7,LR} \n"
17 " LDR R6, =0x5190 \n"
18
19 "loc_FFC4B234:\n"
20 " LDR R0, [R6, #8] \n"
21 " MOV R2, #0 \n"
22 " MOV R1, SP \n"
23 " BL sub_FFC1693C /*_ReceiveMessageQueue*/ \n"
24 " TST R0, #1 \n"
25 " BEQ loc_FFC4B260 \n"
26 " LDR R1, =0x539 \n"
27 " LDR R0, =0xFFC4AE40 /*'SsShootTask.c'*/ \n"
28 " BL _DebugAssert \n"
29 " BL _ExitTask \n"
30 " LDMFD SP!, {R3-R7,PC} \n"
31
32 "loc_FFC4B260:\n"
33 " LDR R0, [SP] \n"
34 " LDR R1, [R0] \n"
35 " CMP R1, #0x1D \n"
36 " ADDLS PC, PC, R1, LSL#2 \n"
37 " B loc_FFC4B42C \n"
38 " B loc_FFC4B2EC \n"
39 " B loc_FFC4B2F4 \n"
40 " B loc_FFC4B2FC \n"
41 " B loc_FFC4B310 \n"
42 " B loc_FFC4B308 \n"
43 " B loc_FFC4B318 \n"
44 " B loc_FFC4B320 \n"
45 " B loc_FFC4B32C \n"
46 " B loc_FFC4B384 \n"
47 " B loc_FFC4B310 \n"
48 " B loc_FFC4B38C \n"
49 " B loc_FFC4B39C \n"
50 " B loc_FFC4B3A4 \n"
51 " B loc_FFC4B3AC \n"
52 " B loc_FFC4B3B4 \n"
53 " B loc_FFC4B3BC \n"
54 " B loc_FFC4B3C4 \n"
55 " B loc_FFC4B3CC \n"
56 " B loc_FFC4B3D8 \n"
57 " B loc_FFC4B3E0 \n"
58 " B loc_FFC4B3E8 \n"
59 " B loc_FFC4B3F0 \n"
60 " B loc_FFC4B3F8 \n"
61 " B loc_FFC4B404 \n"
62 " B loc_FFC4B40C \n"
63 " B loc_FFC4B414 \n"
64 " B loc_FFC4B41C \n"
65 " B loc_FFC4B424 \n"
66 " B loc_FFC4B438 \n"
67 " B loc_FFC4B438 \n"
68
69 "loc_FFC4B2EC:\n"
70 " BL sub_FFC4BAB8 \n"
71 " BL shooting_expo_param_override\n"
72 " B loc_FFC4B324 \n"
73
74 "loc_FFC4B2F4:\n"
75 " BL sub_FFC4B554_my \n"
76 " B loc_FFC4B438 \n"
77
78 "loc_FFC4B2FC:\n"
79 " MOV R0, #1 \n"
80 " BL sub_FFC4BC54 \n"
81 " B loc_FFC4B438 \n"
82
83 "loc_FFC4B308:\n"
84 " BL sub_FFC4B738 \n"
85 " B loc_FFC4B438 \n"
86
87 "loc_FFC4B310:\n"
88 " BL sub_FFC4BA98 \n"
89 " B loc_FFC4B438 \n"
90
91 "loc_FFC4B318:\n"
92 " BL sub_FFC4BAA0 \n"
93 " B loc_FFC4B438 \n"
94
95 "loc_FFC4B320:\n"
96 " BL sub_FFC4BB74 \n"
97
98 "loc_FFC4B324:\n"
99 " BL sub_FFC4959C \n"
100 " B loc_FFC4B438 \n"
101
102 "loc_FFC4B32C:\n"
103 " LDR R4, [R0, #0xC] \n"
104 " BL sub_FFC4BAA8 \n"
105 " MOV R0, R4 \n"
106 " BL sub_FFD0B3CC \n"
107 " TST R0, #1 \n"
108 " MOV R5, R0 \n"
109 " BNE loc_FFC4B36C \n"
110 " BL sub_FFC5965C \n"
111 " STR R0, [R4, #0x18] \n"
112 " MOV R0, R4 \n"
113 " BL sub_FFD0C1BC \n"
114 " MOV R0, R4 \n"
115 " BL sub_FFD0C670 \n"
116 " MOV R5, R0 \n"
117 " LDR R0, [R4, #0x18] \n"
118 " BL sub_FFC59870 \n"
119
120 "loc_FFC4B36C:\n"
121 " BL sub_FFC4BA98 \n"
122 " MOV R2, R4 \n"
123 " MOV R1, #9 \n"
124 " MOV R0, R5 \n"
125 " BL sub_FFC49978 \n"
126 " B loc_FFC4B438 \n"
127
128 "loc_FFC4B384:\n"
129 " BL sub_FFC4BBD4 \n"
130 " B loc_FFC4B324 \n"
131
132 "loc_FFC4B38C:\n"
133 " LDR R0, =0x18C90 \n"
134 " LDR R0, [R0, #0x4C] \n"
135 " BL sub_FFC4BF6C \n"
136 " B loc_FFC4B438 \n"
137
138 "loc_FFC4B39C:\n"
139 " BL sub_FFC4C214 \n"
140 " B loc_FFC4B438 \n"
141
142 "loc_FFC4B3A4:\n"
143 " BL sub_FFC4C2A0 \n"
144 " B loc_FFC4B438 \n"
145
146 "loc_FFC4B3AC:\n"
147 " BL sub_FFD0B5F0 \n"
148 " B loc_FFC4B438 \n"
149
150 "loc_FFC4B3B4:\n"
151 " BL sub_FFD0B7D8 \n"
152 " B loc_FFC4B438 \n"
153
154 "loc_FFC4B3BC:\n"
155 " BL sub_FFD0B868 \n"
156 " B loc_FFC4B438 \n"
157
158 "loc_FFC4B3C4:\n"
159 " BL sub_FFD0B910 \n"
160 " B loc_FFC4B438 \n"
161
162 "loc_FFC4B3CC:\n"
163 " MOV R0, #0 \n"
164 " BL sub_FFD0BAB4 \n"
165 " B loc_FFC4B438 \n"
166
167 "loc_FFC4B3D8:\n"
168 " BL sub_FFD0BBF4 \n"
169 " B loc_FFC4B438 \n"
170
171 "loc_FFC4B3E0:\n"
172 " BL sub_FFD0BC88 \n"
173 " B loc_FFC4B438 \n"
174
175 "loc_FFC4B3E8:\n"
176 " BL sub_FFD0BD4C \n"
177 " B loc_FFC4B438 \n"
178
179 "loc_FFC4B3F0:\n"
180 " BL sub_FFC4BDBC \n"
181 " B loc_FFC4B438 \n"
182
183 "loc_FFC4B3F8:\n"
184 " BL sub_FFC4BDE8 \n"
185 " BL sub_FFC1416C \n"
186 " B loc_FFC4B438 \n"
187
188 "loc_FFC4B404:\n"
189 " BL sub_FFD0B9CC \n"
190 " B loc_FFC4B438 \n"
191
192 "loc_FFC4B40C:\n"
193 " BL sub_FFD0BA10 \n"
194 " B loc_FFC4B438 \n"
195
196 "loc_FFC4B414:\n"
197 " BL sub_FFC4D74C \n"
198 " B loc_FFC4B438 \n"
199
200 "loc_FFC4B41C:\n"
201 " BL sub_FFC4D768 \n"
202 " B loc_FFC4B438 \n"
203
204 "loc_FFC4B424:\n"
205 " BL sub_FFC4D778 \n"
206 " B loc_FFC4B438 \n"
207
208 "loc_FFC4B42C:\n"
209 " LDR R1, =0x65E \n"
210 " LDR R0, =0xFFC4AE40 /*'SsShootTask.c'*/ \n"
211 " BL _DebugAssert \n"
212
213 "loc_FFC4B438:\n"
214 " LDR R0, [SP] \n"
215 " LDR R1, [R0, #4] \n"
216 " LDR R0, [R6, #4] \n"
217 " BL sub_FFC166AC /*_SetEventFlag*/ \n"
218 " LDR R4, [SP] \n"
219 " LDR R0, [R4, #8] \n"
220 " CMP R0, #0 \n"
221 " LDREQ R1, =0x11D \n"
222 " LDREQ R0, =0xFFC4AE40 /*'SsShootTask.c'*/ \n"
223 " BLEQ _DebugAssert \n"
224 " MOV R0, #0 \n"
225 " STR R0, [R4, #8] \n"
226 " B loc_FFC4B234 \n"
227 );
228 }
229
230
231
232 void __attribute__((naked,noinline)) sub_FFC4B554_my() {
233 asm volatile (
234 " STMFD SP!, {R3-R5,LR} \n"
235 " LDR R4, [R0, #0xC] \n"
236 " LDR R0, [R4, #8] \n"
237 " ORR R0, R0, #1 \n"
238 " STR R0, [R4, #8] \n"
239 " MOV R0, #2 \n"
240 " BL sub_FFC462C8 \n"
241 " BL sub_FFC4BAA8 \n"
242 " MOV R0, R4 \n"
243 " BL sub_FFC4BD70 \n"
244 " MOV R0, R4 \n"
245 " BL sub_FFD0B054 \n"
246 " CMP R0, #0 \n"
247 " MOV R0, R4 \n"
248 " BEQ loc_FFC4B5AC \n"
249 " BL sub_FFD0B0F0 \n"
250 " TST R0, #1 \n"
251 " MOVNE R2, R4 \n"
252 " LDMNEFD SP!, {R3-R5,LR} \n"
253 " MOVNE R1, #1 \n"
254 " BNE sub_FFC49978 \n"
255 " B loc_FFC4B5B0 \n"
256
257 "loc_FFC4B5AC:\n"
258 " BL sub_FFD0B0A4 \n"
259
260 "loc_FFC4B5B0:\n"
261 " MOV R0, #0 \n"
262 " STR R0, [SP] \n"
263 " LDR R0, =0x18C90 \n"
264 " MOV R2, #2 \n"
265 " LDRH R0, [R0, #0x8A] \n"
266 " MOV R1, SP \n"
267 " CMP R0, #3 \n"
268 " LDRNE R0, [R4, #0xC] \n"
269 " CMPNE R0, #1 \n"
270 " MOVHI R0, #1 \n"
271 " STRHI R0, [SP] \n"
272 " LDR R0, =0x123 \n"
273 " BL _SetPropertyCase \n"
274 " BL sub_FFD2D9BC \n"
275 " BL sub_FFC5965C \n"
276 " STR R0, [R4, #0x18] \n"
277 " MOV R0, R4 \n"
278 " BL sub_FFD0C1BC \n"
279 " BL sub_FFD0CD0C \n"
280 " MOV R0, R4 \n"
281 " BL sub_FFD0C284_my \n"
282 " MOV R5, R0 \n"
283 " BL capt_seq_hook_raw_here\n"
284 " BL sub_FFC4D768 \n"
285 " BL sub_FFC4D7A4 \n"
286 " MOV R2, R4 \n"
287 " MOV R1, #1 \n"
288 " MOV R0, R5 \n"
289 " BL sub_FFC49978 \n"
290 " BL sub_FFD0C600 \n"
291 " CMP R0, #0 \n"
292 " LDRNE R0, [R4, #8] \n"
293 " ORRNE R0, R0, #0x2000 \n"
294 " STRNE R0, [R4, #8] \n"
295 " LDMFD SP!, {R3-R5,PC} \n"
296 );
297 }
298
299
300
301 void __attribute__((naked,noinline)) sub_FFD0C284_my() {
302 asm volatile (
303 " STMFD SP!, {R1-R9,LR} \n"
304 " MOV R4, R0 \n"
305 " BL sub_FFD0CE6C \n"
306 " MVN R1, #0 \n"
307 " BL sub_FFC166E0 /*_ClearEventFlag*/ \n"
308 " MOV R2, #4 \n"
309 " ADD R1, SP, #4 \n"
310 " MOV R0, #0x8A \n"
311 " BL _GetPropertyCase \n"
312 " TST R0, #1 \n"
313 " MOVNE R1, #0x35C \n"
314 " LDRNE R0, =0xFFD0C3FC /*'SsCaptureSeq.c'*/ \n"
315 " BLNE _DebugAssert \n"
316 " LDR R7, =0x18D48 \n"
317 " LDR R6, =0x18C90 \n"
318 " LDRSH R1, [R7, #0xE] \n"
319 " LDR R0, [R6, #0x80] \n"
320 " BL sub_FFDC18E0 \n"
321 " BL _GetCCDTemperature \n"
322 " LDR R3, =0x8598 \n"
323 " STRH R0, [R4, #0x94] \n"
324 " STR R3, [SP] \n"
325 " MOV R1, R0 \n"
326 " LDRH R0, [R6, #0x54] \n"
327 " LDRSH R2, [R7, #0xC] \n"
328 " SUB R3, R3, #4 \n"
329 " BL sub_FFD0D464 \n"
330 " BL wait_until_remote_button_is_released\n"
331 " BL capt_seq_hook_set_nr\n"
332 " LDR PC, =0xFFD0C2F0 \n"
333 );
334 }
335
336
337
338 void __attribute__((naked,noinline)) exp_drv_task() {
339 asm volatile (
340 " STMFD SP!, {R4-R8,LR} \n"
341 " SUB SP, SP, #0x20 \n"
342 " LDR R8, =0xBB8 \n"
343 " LDR R7, =0x6258 \n"
344 " LDR R5, =0x1DBD8 \n"
345 " MOV R0, #0 \n"
346 " ADD R6, SP, #0x10 \n"
347 " STR R0, [SP, #0xC] \n"
348
349 "loc_FFC84268:\n"
350 " LDR R0, [R7, #0x20] \n"
351 " MOV R2, #0 \n"
352 " ADD R1, SP, #0x1C \n"
353 " BL sub_FFC1693C /*_ReceiveMessageQueue*/ \n"
354 " LDR R0, [SP, #0xC] \n"
355 " CMP R0, #1 \n"
356 " BNE loc_FFC842B0 \n"
357 " LDR R0, [SP, #0x1C] \n"
358 " LDR R0, [R0] \n"
359 " CMP R0, #0x13 \n"
360 " CMPNE R0, #0x14 \n"
361 " CMPNE R0, #0x15 \n"
362 " BEQ loc_FFC843CC \n"
363 " CMP R0, #0x27 \n"
364 " BEQ loc_FFC843A4 \n"
365 " ADD R1, SP, #0xC \n"
366 " MOV R0, #0 \n"
367 " BL sub_FFC841F8 \n"
368
369 "loc_FFC842B0:\n"
370 " LDR R0, [SP, #0x1C] \n"
371 " LDR R1, [R0] \n"
372 " CMP R1, #0x2C \n"
373 " BNE loc_FFC842E0 \n"
374 " LDR R0, [SP, #0x1C] \n"
375 " BL sub_FFC854B4 \n"
376 " LDR R0, [R7, #0x1C] \n"
377 " MOV R1, #1 \n"
378 " BL sub_FFC166AC /*_SetEventFlag*/ \n"
379 " BL _ExitTask \n"
380 " ADD SP, SP, #0x20 \n"
381 " LDMFD SP!, {R4-R8,PC} \n"
382
383 "loc_FFC842E0:\n"
384 " CMP R1, #0x2B \n"
385 " BNE loc_FFC842FC \n"
386 " LDR R2, [R0, #0x88]! \n"
387 " LDR R1, [R0, #4] \n"
388 " MOV R0, R1 \n"
389 " BLX R2 \n"
390 " B loc_FFC84838 \n"
391
392 "loc_FFC842FC:\n"
393 " CMP R1, #0x25 \n"
394 " BNE loc_FFC8434C \n"
395 " LDR R0, [R7, #0x1C] \n"
396 " MOV R1, #0x80 \n"
397 " BL sub_FFC166E0 /*_ClearEventFlag*/ \n"
398 " LDR R0, =0xFFC80D04 \n"
399 " MOV R1, #0x80 \n"
400 " BL sub_FFD002E8 \n"
401 " LDR R0, [R7, #0x1C] \n"
402 " MOV R2, R8 \n"
403 " MOV R1, #0x80 \n"
404 " BL sub_FFC165EC /*_WaitForAllEventFlag*/ \n"
405 " TST R0, #1 \n"
406 " LDRNE R1, =0xD36 \n"
407 " BNE loc_FFC84390 \n"
408
409 "loc_FFC84338:\n"
410 " LDR R1, [SP, #0x1C] \n"
411 " LDR R0, [R1, #0x8C] \n"
412 " LDR R1, [R1, #0x88] \n"
413 " BLX R1 \n"
414 " B loc_FFC84838 \n"
415
416 "loc_FFC8434C:\n"
417 " CMP R1, #0x26 \n"
418 " BNE loc_FFC8439C \n"
419 " ADD R1, SP, #0xC \n"
420 " BL sub_FFC841F8 \n"
421 " LDR R0, [R7, #0x1C] \n"
422 " MOV R1, #0x100 \n"
423 " BL sub_FFC166E0 /*_ClearEventFlag*/ \n"
424 " LDR R0, =0xFFC80D14 \n"
425 " MOV R1, #0x100 \n"
426 " BL sub_FFD00570 \n"
427 " LDR R0, [R7, #0x1C] \n"
428 " MOV R2, R8 \n"
429 " MOV R1, #0x100 \n"
430 " BL sub_FFC165EC /*_WaitForAllEventFlag*/ \n"
431 " TST R0, #1 \n"
432 " BEQ loc_FFC84338 \n"
433 " MOV R1, #0xD40 \n"
434
435 "loc_FFC84390:\n"
436 " LDR R0, =0xFFC81404 /*'ExpDrv.c'*/ \n"
437 " BL _DebugAssert \n"
438 " B loc_FFC84338 \n"
439
440 "loc_FFC8439C:\n"
441 " CMP R1, #0x27 \n"
442 " BNE loc_FFC843B4 \n"
443
444 "loc_FFC843A4:\n"
445 " LDR R0, [SP, #0x1C] \n"
446 " ADD R1, SP, #0xC \n"
447 " BL sub_FFC841F8 \n"
448 " B loc_FFC84338 \n"
449
450 "loc_FFC843B4:\n"
451 " CMP R1, #0x2A \n"
452 " BNE loc_FFC843CC \n"
453 " BL sub_FFC6E710 \n"
454 " BL sub_FFC6F39C \n"
455 " BL sub_FFC6EED4 \n"
456 " B loc_FFC84338 \n"
457
458 "loc_FFC843CC:\n"
459 " LDR R0, [SP, #0x1C] \n"
460 " MOV R4, #1 \n"
461 " LDR R1, [R0] \n"
462 " CMP R1, #0x11 \n"
463 " CMPNE R1, #0x12 \n"
464 " BNE loc_FFC8443C \n"
465 " LDR R1, [R0, #0x7C] \n"
466 " ADD R1, R1, R1, LSL#1 \n"
467 " ADD R1, R0, R1, LSL#2 \n"
468 " SUB R1, R1, #8 \n"
469 " LDMIA R1, {R2-R4} \n"
470 " STMIA R6, {R2-R4} \n"
471 " BL sub_FFC82D84 \n"
472 " LDR R0, [SP, #0x1C] \n"
473 " LDR R1, [R0, #0x7C] \n"
474 " LDR R3, [R0, #0x88] \n"
475 " LDR R2, [R0, #0x8C] \n"
476 " ADD R0, R0, #4 \n"
477 " BLX R3 \n"
478 " LDR R0, [SP, #0x1C] \n"
479 " BL sub_FFC8588C \n"
480 " LDR R0, [SP, #0x1C] \n"
481 " LDR R1, [R0, #0x7C] \n"
482 " LDR R3, [R0, #0x90] \n"
483 " LDR R2, [R0, #0x94] \n"
484 " ADD R0, R0, #4 \n"
485 " BLX R3 \n"
486 " B loc_FFC84778 \n"
487
488 "loc_FFC8443C:\n"
489 " CMP R1, #0x13 \n"
490 " CMPNE R1, #0x14 \n"
491 " CMPNE R1, #0x15 \n"
492 " BNE loc_FFC844F0 \n"
493 " ADD R3, SP, #0xC \n"
494 " MOV R2, SP \n"
495 " ADD R1, SP, #0x10 \n"
496 " BL sub_FFC82FCC \n"
497 " CMP R0, #1 \n"
498 " MOV R4, R0 \n"
499 " CMPNE R4, #5 \n"
500 " BNE loc_FFC8448C \n"
501 " LDR R0, [SP, #0x1C] \n"
502 " MOV R2, R4 \n"
503 " LDR R1, [R0, #0x7C]! \n"
504 " LDR R12, [R0, #0xC]! \n"
505 " LDR R3, [R0, #4] \n"
506 " MOV R0, SP \n"
507 " BLX R12 \n"
508 " B loc_FFC844C4 \n"
509
510 "loc_FFC8448C:\n"
511 " LDR R0, [SP, #0x1C] \n"
512 " CMP R4, #2 \n"
513 " LDR R3, [R0, #0x8C] \n"
514 " CMPNE R4, #6 \n"
515 " BNE loc_FFC844D8 \n"
516 " LDR R12, [R0, #0x88] \n"
517 " MOV R0, SP \n"
518 " MOV R2, R4 \n"
519 " MOV R1, #1 \n"
520 " BLX R12 \n"
521 " LDR R0, [SP, #0x1C] \n"
522 " MOV R2, SP \n"
523 " ADD R1, SP, #0x10 \n"
524 " BL sub_FFC83F44 \n"
525
526 "loc_FFC844C4:\n"
527 " LDR R0, [SP, #0x1C] \n"
528 " LDR R2, [SP, #0xC] \n"
529 " MOV R1, R4 \n"
530 " BL sub_FFC84198 \n"
531 " B loc_FFC84778 \n"
532
533 "loc_FFC844D8:\n"
534 " LDR R1, [R0, #0x7C] \n"
535 " LDR R12, [R0, #0x88] \n"
536 " ADD R0, R0, #4 \n"
537 " MOV R2, R4 \n"
538 " BLX R12 \n"
539 " B loc_FFC84778 \n"
540
541 "loc_FFC844F0:\n"
542 " CMP R1, #0x21 \n"
543 " CMPNE R1, #0x22 \n"
544 " BNE loc_FFC8453C \n"
545 " LDR R1, [R0, #0x7C] \n"
546 " ADD R1, R1, R1, LSL#1 \n"
547 " ADD R1, R0, R1, LSL#2 \n"
548 " SUB R1, R1, #8 \n"
549 " LDMIA R1, {R2-R4} \n"
550 " STMIA R6, {R2-R4} \n"
551 " BL sub_FFC82310 \n"
552 " LDR R0, [SP, #0x1C] \n"
553 " LDR R1, [R0, #0x7C] \n"
554 " LDR R3, [R0, #0x88] \n"
555 " LDR R2, [R0, #0x8C] \n"
556 " ADD R0, R0, #4 \n"
557 " BLX R3 \n"
558 " LDR R0, [SP, #0x1C] \n"
559 " BL sub_FFC82600 \n"
560 " B loc_FFC84778 \n"
561
562 "loc_FFC8453C:\n"
563 " ADD R1, R0, #4 \n"
564 " LDMIA R1, {R2,R3,R12} \n"
565 " STMIA R6, {R2,R3,R12} \n"
566 " LDR R1, [R0] \n"
567 " CMP R1, #0x24 \n"
568 " ADDLS PC, PC, R1, LSL#2 \n"
569 " B loc_FFC84758 \n"
570 " B loc_FFC845EC \n"
571 " B loc_FFC845EC \n"
572 " B loc_FFC84640 \n"
573 " B loc_FFC84648 \n"
574 " B loc_FFC84648 \n"
575 " B loc_FFC84648 \n"
576 " B loc_FFC845EC \n"
577 " B loc_FFC84640 \n"
578 " B loc_FFC84648 \n"
579 " B loc_FFC84648 \n"
580 " B loc_FFC84660 \n"
581 " B loc_FFC84660 \n"
582 " B loc_FFC8474C \n"
583 " B loc_FFC84754 \n"
584 " B loc_FFC84754 \n"
585 " B loc_FFC84754 \n"
586 " B loc_FFC84754 \n"
587 " B loc_FFC84758 \n"
588 " B loc_FFC84758 \n"
589 " B loc_FFC84758 \n"
590 " B loc_FFC84758 \n"
591 " B loc_FFC84758 \n"
592 " B loc_FFC84650 \n"
593 " B loc_FFC84658 \n"
594 " B loc_FFC84658 \n"
595 " B loc_FFC8466C \n"
596 " B loc_FFC8466C \n"
597 " B loc_FFC84674 \n"
598 " B loc_FFC846A4 \n"
599 " B loc_FFC846D4 \n"
600 " B loc_FFC84704 \n"
601 " B loc_FFC84734 \n"
602 " B loc_FFC84734 \n"
603 " B loc_FFC84758 \n"
604 " B loc_FFC84758 \n"
605 " B loc_FFC8473C \n"
606 " B loc_FFC84744 \n"
607
608 "loc_FFC845EC:\n"
609 " BL sub_FFC811F0 \n"
610 " B loc_FFC84758 \n"
611
612 "loc_FFC84640:\n"
613 " BL sub_FFC81478 \n"
614 " B loc_FFC84758 \n"
615
616 "loc_FFC84648:\n"
617 " BL sub_FFC8167C \n"
618 " B loc_FFC84758 \n"
619
620 "loc_FFC84650:\n"
621 " BL sub_FFC818E4 \n"
622 " B loc_FFC84758 \n"
623
624 "loc_FFC84658:\n"
625 " BL sub_FFC81AD8 \n"
626 " B loc_FFC84758 \n"
627
628 "loc_FFC84660:\n"
629 " BL sub_FFC81D40_my \n"
630 " MOV R4, #0 \n"
631 " B loc_FFC84758 \n"
632
633 "loc_FFC8466C:\n"
634 " BL sub_FFC81E7C \n"
635 " B loc_FFC84758 \n"
636
637 "loc_FFC84674:\n"
638 " LDRH R1, [R0, #4] \n"
639 " STRH R1, [SP, #0x10] \n"
640 " LDRH R1, [R5, #2] \n"
641 " STRH R1, [SP, #0x12] \n"
642 " LDRH R1, [R5, #4] \n"
643 " STRH R1, [SP, #0x14] \n"
644 " LDRH R1, [R5, #6] \n"
645 " STRH R1, [SP, #0x16] \n"
646 " LDRH R1, [R0, #0xC] \n"
647 " STRH R1, [SP, #0x18] \n"
648 " BL sub_FFC85528 \n"
649 " B loc_FFC84758 \n"
650
651 "loc_FFC846A4:\n"
652 " LDRH R1, [R0, #4] \n"
653 " STRH R1, [SP, #0x10] \n"
654 " LDRH R1, [R5, #2] \n"
655 " STRH R1, [SP, #0x12] \n"
656 " LDRH R1, [R5, #4] \n"
657 " STRH R1, [SP, #0x14] \n"
658 " LDRH R1, [R5, #6] \n"
659 " STRH R1, [SP, #0x16] \n"
660 " LDRH R1, [R5, #8] \n"
661 " STRH R1, [SP, #0x18] \n"
662 " BL sub_FFC856A8 \n"
663 " B loc_FFC84758 \n"
664
665 "loc_FFC846D4:\n"
666 " LDRH R1, [R5] \n"
667 " STRH R1, [SP, #0x10] \n"
668 " LDRH R1, [R0, #6] \n"
669 " STRH R1, [SP, #0x12] \n"
670 " LDRH R1, [R5, #4] \n"
671 " STRH R1, [SP, #0x14] \n"
672 " LDRH R1, [R5, #6] \n"
673 " STRH R1, [SP, #0x16] \n"
674 " LDRH R1, [R5, #8] \n"
675 " STRH R1, [SP, #0x18] \n"
676 " BL sub_FFC85754 \n"
677 " B loc_FFC84758 \n"
678
679 "loc_FFC84704:\n"
680 " LDRH R1, [R5] \n"
681 " STRH R1, [SP, #0x10] \n"
682 " LDRH R1, [R5, #2] \n"
683 " STRH R1, [SP, #0x12] \n"
684 " LDRH R1, [R5, #4] \n"
685 " STRH R1, [SP, #0x14] \n"
686 " LDRH R1, [R5, #6] \n"
687 " STRH R1, [SP, #0x16] \n"
688 " LDRH R1, [R0, #0xC] \n"
689 " STRH R1, [SP, #0x18] \n"
690 " BL sub_FFC857F4 \n"
691 " B loc_FFC84758 \n"
692
693 "loc_FFC84734:\n"
694 " BL sub_FFC820F0 \n"
695 " B loc_FFC84758 \n"
696
697 "loc_FFC8473C:\n"
698 " BL sub_FFC82704 \n"
699 " B loc_FFC84758 \n"
700
701 "loc_FFC84744:\n"
702 " BL sub_FFC8293C \n"
703 " B loc_FFC84758 \n"
704
705 "loc_FFC8474C:\n"
706 " BL sub_FFC82AB4 \n"
707 " B loc_FFC84758 \n"
708
709 "loc_FFC84754:\n"
710 " BL sub_FFC82C4C \n"
711
712 "loc_FFC84758:\n"
713 " LDR R0, [SP, #0x1C] \n"
714 " LDR R1, [R0, #0x7C] \n"
715 " LDR R3, [R0, #0x88] \n"
716 " LDR R2, [R0, #0x8C] \n"
717 " ADD R0, R0, #4 \n"
718 " BLX R3 \n"
719 " CMP R4, #1 \n"
720 " BNE loc_FFC847C0 \n"
721
722 "loc_FFC84778:\n"
723 " LDR R0, [SP, #0x1C] \n"
724 " MOV R2, #0xC \n"
725 " LDR R1, [R0, #0x7C] \n"
726 " ADD R1, R1, R1, LSL#1 \n"
727 " ADD R0, R0, R1, LSL#2 \n"
728 " SUB R4, R0, #8 \n"
729 " LDR R0, =0x1DBD8 \n"
730 " ADD R1, SP, #0x10 \n"
731 " BL sub_FFE715DC \n"
732 " LDR R0, =0x1DBE4 \n"
733 " MOV R2, #0xC \n"
734 " ADD R1, SP, #0x10 \n"
735 " BL sub_FFE715DC \n"
736 " LDR R0, =0x1DBF0 \n"
737 " MOV R2, #0xC \n"
738 " MOV R1, R4 \n"
739 " BL sub_FFE715DC \n"
740 " B loc_FFC84838 \n"
741
742 "loc_FFC847C0:\n"
743 " LDR R0, [SP, #0x1C] \n"
744 " LDR R0, [R0] \n"
745 " CMP R0, #0xB \n"
746 " BNE loc_FFC84808 \n"
747 " MOV R3, #0 \n"
748 " STR R3, [SP] \n"
749 " MOV R3, #1 \n"
750 " MOV R2, #1 \n"
751 " MOV R1, #1 \n"
752 " MOV R0, #0 \n"
753 " BL sub_FFC80FF8 \n"
754 " MOV R3, #0 \n"
755 " STR R3, [SP] \n"
756 " MOV R3, #1 \n"
757 " MOV R2, #1 \n"
758 " MOV R1, #1 \n"
759 " MOV R0, #0 \n"
760 " B loc_FFC84834 \n"
761
762 "loc_FFC84808:\n"
763 " MOV R3, #1 \n"
764 " MOV R2, #1 \n"
765 " MOV R1, #1 \n"
766 " MOV R0, #1 \n"
767 " STR R3, [SP] \n"
768 " BL sub_FFC80FF8 \n"
769 " MOV R3, #1 \n"
770 " MOV R2, #1 \n"
771 " MOV R1, #1 \n"
772 " MOV R0, #1 \n"
773 " STR R3, [SP] \n"
774
775 "loc_FFC84834:\n"
776 " BL sub_FFC81138 \n"
777
778 "loc_FFC84838:\n"
779 " LDR R0, [SP, #0x1C] \n"
780 " BL sub_FFC854B4 \n"
781 " B loc_FFC84268 \n"
782 );
783 }
784
785
786
787 void __attribute__((naked,noinline)) sub_FFC81D40_my() {
788 asm volatile (
789 " STMFD SP!, {R4-R8,LR} \n"
790 " LDR R7, =0x6258 \n"
791 " MOV R4, R0 \n"
792 " LDR R0, [R7, #0x1C] \n"
793 " MOV R1, #0x3E \n"
794 " BL sub_FFC166E0 /*_ClearEventFlag*/ \n"
795 " LDRSH R0, [R4, #4] \n"
796 " MOV R2, #0 \n"
797 " MOV R1, #0 \n"
798 " BL sub_FFC80D88 \n"
799 " MOV R6, R0 \n"
800 " LDRSH R0, [R4, #6] \n"
801 " BL sub_FFC80E98 \n"
802 " LDRSH R0, [R4, #8] \n"
803 " BL sub_FFC80EF0 \n"
804 " LDRSH R0, [R4, #0xA] \n"
805 " BL sub_FFC80F48 \n"
806 " LDRSH R0, [R4, #0xC] \n"
807 " BL sub_FFC80FA0 \n"
808 " MOV R5, R0 \n"
809 " LDR R0, [R4] \n"
810 " LDR R8, =0x1DBF0 \n"
811 " CMP R0, #0xB \n"
812 " MOVEQ R6, #0 \n"
813 " MOVEQ R5, #0 \n"
814 " BEQ loc_FFC81DD0 \n"
815 " CMP R6, #1 \n"
816 " BNE loc_FFC81DD0 \n"
817 " LDRSH R0, [R4, #4] \n"
818 " LDR R1, =0xFFC80CF4 \n"
819 " MOV R2, #2 \n"
820 " BL sub_FFD0043C \n"
821 " STRH R0, [R4, #4] \n"
822 " MOV R0, #0 \n"
823 " STR R0, [R7, #0x28] \n"
824 " B loc_FFC81DD8 \n"
825
826 "loc_FFC81DD0:\n"
827 " LDRH R0, [R8] \n"
828 " STRH R0, [R4, #4] \n"
829
830 "loc_FFC81DD8:\n"
831 " CMP R5, #1 \n"
832 " LDRNEH R0, [R8, #8] \n"
833 " BNE loc_FFC81DF4 \n"
834 " LDRSH R0, [R4, #0xC] \n"
835 " LDR R1, =0xFFC80D78 \n"
836 " MOV R2, #0x20 \n"
837 " BL sub_FFC854E4 \n"
838
839 "loc_FFC81DF4:\n"
840 " STRH R0, [R4, #0xC] \n"
841 " LDRSH R0, [R4, #6] \n"
842 " BL sub_FFC6E480_my \n"
843 " LDR PC, =0xFFC81E00 \n"
844 );
845 }
846
847
848
849 void __attribute__((naked,noinline)) sub_FFC6E480_my() {
850 asm volatile (
851 " STMFD SP!, {R4-R6,LR} \n"
852 " LDR R5, =0x5F0C \n"
853 " MOV R4, R0 \n"
854 " LDR R0, [R5, #4] \n"
855 " CMP R0, #1 \n"
856 " MOVNE R1, #0x140 \n"
857 " LDRNE R0, =0xFFC6E284 /*'Shutter.c'*/ \n"
858 " BLNE _DebugAssert \n"
859 " CMN R4, #0xC00 \n"
860 " LDREQSH R4, [R5, #2] \n"
861 " CMN R4, #0xC00 \n"
862 " LDREQ R1, =0x146 \n"
863 " LDREQ R0, =0xFFC6E284 /*'Shutter.c'*/ \n"
864 " STRH R4, [R5, #2] \n"
865 " BLEQ _DebugAssert \n"
866 " MOV R0, R4 \n"
867 " BL apex2us \n"
868 " MOV R4, R0 \n"
869
870 " MOV R0, R4 \n"
871 " BL sub_FFCA3474 \n"
872 " TST R0, #1 \n"
873 " LDRNE R1, =0x14B \n"
874 " LDMNEFD SP!, {R4-R6,LR} \n"
875 " LDRNE R0, =0xFFC6E284 /*'Shutter.c'*/ \n"
876 " BNE _DebugAssert \n"
877 " LDMFD SP!, {R4-R6,PC} \n"
878 );
879 }