This source file includes following definitions.
- filewritetask
- sub_FFDC1144_my
- sub_FFDC1284_my
- sub_FFDC1380_my
1
2
3
4 #include "lolevel.h"
5 #include "platform.h"
6
7 typedef struct {
8 unsigned int address;
9 unsigned int length;
10 } cam_ptp_data_chunk;
11
12 #define MAX_CHUNKS_FOR_FWT 3
13
14
15
16
17
18
19
20 typedef struct
21 {
22 int unkn1[5];
23 cam_ptp_data_chunk pdc[MAX_CHUNKS_FOR_FWT];
24 char name[32];
25
26 } fwt_data_struct;
27
28 #include "../../../generic/filewrite.c"
29
30
31
32 void __attribute__((naked,noinline)) filewritetask() {
33 asm volatile (
34 " STMFD SP!, {R1-R5,LR} \n"
35 " LDR R4, =0xC078 \n"
36
37 "loc_FFDC0EAC:\n"
38 " LDR R0, [R4, #0x10] \n"
39 " MOV R2, #0 \n"
40 " ADD R1, SP, #8 \n"
41 " BL sub_FFC1763C /*_ReceiveMessageQueue*/ \n"
42 " CMP R0, #0 \n"
43 " BNE loc_FFDC0EDC \n"
44 " LDR R0, [SP, #8] \n"
45 " LDR R1, [R0] \n"
46 " CMP R1, #1 \n"
47 " BNE loc_FFDC0EE4 \n"
48 " LDR R0, [R4, #8] \n"
49 " BL _GiveSemaphore \n"
50
51 "loc_FFDC0EDC:\n"
52 " BL _ExitTask \n"
53 " LDMFD SP!, {R1-R5,PC} \n"
54
55 "loc_FFDC0EE4:\n"
56 " SUB R1, R1, #2 \n"
57 " CMP R1, #5 \n"
58 " ADDLS PC, PC, R1, LSL#2 \n"
59 " B loc_FFDC0EAC \n"
60 " B loc_FFDC0F0C \n"
61 " B loc_FFDC0F70 \n"
62 " B loc_FFDC0F78 \n"
63 " B loc_FFDC0F78 \n"
64 " B loc_FFDC0F78 \n"
65 " B loc_FFDC0F80 \n"
66
67 "loc_FFDC0F0C:\n"
68 " MOV R0, #0 \n"
69 " STR R0, [SP] \n"
70
71 "loc_FFDC0F14:\n"
72 " LDR R0, [R4, #0x10] \n"
73 " MOV R1, SP \n"
74 " BL sub_FFC17840 /*_GetNumberOfPostedMessages*/ \n"
75 " LDR R0, [SP] \n"
76 " CMP R0, #0 \n"
77 " BEQ loc_FFDC0F40 \n"
78 " LDR R0, [R4, #0x10] \n"
79 " MOV R2, #0 \n"
80 " ADD R1, SP, #4 \n"
81 " BL sub_FFC1763C /*_ReceiveMessageQueue*/ \n"
82 " B loc_FFDC0F14 \n"
83
84 "loc_FFDC0F40:\n"
85 " LDR R0, [R4] \n"
86 " CMN R0, #1 \n"
87 " BEQ loc_FFDC0F64 \n"
88 " BL fwt_close \n"
89 " MVN R0, #0 \n"
90 " STR R0, [R4] \n"
91 " LDR R0, =0x7BA14 \n"
92 " BL sub_FFC3C9D4 \n"
93 " BL sub_FFC3E288 \n"
94
95 "loc_FFDC0F64:\n"
96 " LDR R0, [R4, #0xC] \n"
97 " BL _GiveSemaphore \n"
98 " B loc_FFDC0EAC \n"
99
100 "loc_FFDC0F70:\n"
101 " BL sub_FFDC1144_my \n"
102 " B loc_FFDC0EAC \n"
103
104 "loc_FFDC0F78:\n"
105 " BL sub_FFDC1284_my \n"
106 " B loc_FFDC0EAC \n"
107
108 "loc_FFDC0F80:\n"
109 " BL sub_FFDC1380_my \n"
110 " B loc_FFDC0EAC \n"
111 );
112 }
113
114
115
116 void __attribute__((naked,noinline)) sub_FFDC1144_my() {
117 asm volatile (
118 " STMFD SP!, {R4-R8,LR} \n"
119 " MOV R4, R0 \n"
120 " ADD R0, R0, #0x2C \n"
121 " SUB SP, SP, #0x38 \n"
122 " BL sub_FFC3C9D4 \n"
123 " MOV R1, #0 \n"
124 " BL sub_FFC3E238 \n"
125 " LDR R0, [R4, #0xC] \n"
126 " BL sub_FFC3EB28 \n"
127 " LDR R7, [R4, #8] \n"
128 " LDR R8, =0x1B6 \n"
129 " ADD R6, R4, #0x2C \n"
130 " LDR R5, [R4, #0xC] \n"
131
132 " STMFD SP!, {R4-R12,LR}\n"
133 " MOV R0, R4\n"
134 " BL filewrite_main_hook\n"
135 " LDMFD SP!, {R4-R12,LR}\n"
136
137 " MOV R0, R6 \n"
138 " MOV R1, R7 \n"
139 " MOV R2, R8 \n"
140 " BL fwt_open \n"
141 " LDR PC, =0xFFDC1188 \n"
142 );
143 }
144
145
146
147 void __attribute__((naked,noinline)) sub_FFDC1284_my() {
148 asm volatile (
149 " STMFD SP!, {R4-R10,LR} \n"
150 " MOV R4, R0 \n"
151 " LDR R0, [R0] \n"
152 " CMP R0, #4 \n"
153 " LDREQ R6, [R4, #0x18] \n"
154 " LDREQ R7, [R4, #0x14] \n"
155 " BEQ loc_FFDC12C0 \n"
156 " CMP R0, #5 \n"
157 " LDREQ R6, [R4, #0x20] \n"
158 " LDREQ R7, [R4, #0x1C] \n"
159 " BEQ loc_FFDC12C0 \n"
160 " CMP R0, #6 \n"
161 " BNE loc_FFDC12D4 \n"
162 " LDR R6, [R4, #0x28] \n"
163 " LDR R7, [R4, #0x24] \n"
164
165 "loc_FFDC12C0:\n"
166 " CMP R6, #0 \n"
167 " BNE loc_FFDC12E4 \n"
168
169 "loc_FFDC12C8:\n"
170 " MOV R1, R4 \n"
171 " MOV R0, #7 \n"
172 " B loc_FFDC1378 \n"
173
174 "loc_FFDC12D4:\n"
175 " LDR R1, =0x1E2 \n"
176 " LDR R0, =0xFFDC1264 /*'dwFWrite.c'*/ \n"
177 " BL _DebugAssert \n"
178 " B loc_FFDC12C8 \n"
179
180 "loc_FFDC12E4:\n"
181 " LDR R9, =0xC078 \n"
182 " MOV R5, R6 \n"
183
184 "loc_FFDC12EC:\n"
185 " LDR R0, [R4, #4] \n"
186 " CMP R5, #0x1000000 \n"
187 " MOVLS R8, R5 \n"
188 " MOVHI R8, #0x1000000 \n"
189 " BIC R1, R0, #0xFF000000 \n"
190 " CMP R1, #0 \n"
191 " BICNE R0, R0, #0xFF000000 \n"
192 " RSBNE R0, R0, #0x1000000 \n"
193 " CMPNE R8, R0 \n"
194 " MOVHI R8, R0 \n"
195 " LDR R0, [R9] \n"
196 " MOV R2, R8 \n"
197 " MOV R1, R7 \n"
198 " BL fwt_write \n"
199 " LDR R1, [R4, #4] \n"
200 " CMP R8, R0 \n"
201 " ADD R1, R1, R0 \n"
202 " STR R1, [R4, #4] \n"
203 " BEQ loc_FFDC134C \n"
204 " LDR R0, =0x10B1 \n"
205 " BL sub_FFC5B294 /*_IsControlEventActive_FW*/ \n"
206 " LDR R1, =0x9200005 \n"
207 " STR R1, [R4, #0x10] \n"
208 " B loc_FFDC12C8 \n"
209
210 "loc_FFDC134C:\n"
211 " SUB R5, R5, R0 \n"
212 " CMP R5, R6 \n"
213 " ADD R7, R7, R0 \n"
214 " LDRCS R1, =0x211 \n"
215 " LDRCS R0, =0xFFDC1264 /*'dwFWrite.c'*/ \n"
216 " BLCS _DebugAssert \n"
217 " CMP R5, #0 \n"
218 " BNE loc_FFDC12EC \n"
219 " LDR R0, [R4] \n"
220 " MOV R1, R4 \n"
221 " ADD R0, R0, #1 \n"
222
223 "loc_FFDC1378:\n"
224 " LDMFD SP!, {R4-R10,LR} \n"
225 " B sub_FFDC0DFC \n"
226 );
227 }
228
229
230
231 void __attribute__((naked,noinline)) sub_FFDC1380_my() {
232 asm volatile (
233 " STMFD SP!, {R4,R5,LR} \n"
234 " LDR R5, =0xC078 \n"
235 " MOV R4, R0 \n"
236 " LDR R0, [R5] \n"
237 " SUB SP, SP, #0x1C \n"
238 " CMN R0, #1 \n"
239 " BEQ sub_FFDC13B4 \n"
240 " BL fwt_close \n"
241 " LDR PC, =0xFFDC13A0 \n"
242 );
243 }