This source file includes following definitions.
- filewritetask
- sub_FFDCB848_my
- sub_FFDCB988_my
- sub_FFDCBA84_my
1
2
3
4 #include "lolevel.h"
5 #include "platform.h"
6
7 typedef struct {
8 unsigned int address;
9 unsigned int length;
10 } cam_ptp_data_chunk;
11
12 #define MAX_CHUNKS_FOR_FWT 3
13
14
15
16
17
18
19
20 typedef struct
21 {
22 int unkn1[5];
23 cam_ptp_data_chunk pdc[MAX_CHUNKS_FOR_FWT];
24 char name[32];
25 } fwt_data_struct;
26
27 #include "../../../generic/filewrite.c"
28
29
30
31 void __attribute__((naked,noinline)) filewritetask() {
32 asm volatile (
33 " STMFD SP!, {R1-R5,LR} \n"
34 " LDR R4, =0xAAE4 \n"
35
36 "loc_FFDCB5B0:\n"
37 " LDR R0, [R4, #0x10] \n"
38 " MOV R2, #0 \n"
39 " ADD R1, SP, #8 \n"
40 " BL sub_FFC1764C /*_ReceiveMessageQueue*/ \n"
41 " CMP R0, #0 \n"
42 " BNE loc_FFDCB5E0 \n"
43 " LDR R0, [SP, #8] \n"
44 " LDR R1, [R0] \n"
45 " CMP R1, #1 \n"
46 " BNE loc_FFDCB5E8 \n"
47 " LDR R0, [R4, #8] \n"
48 " BL _GiveSemaphore \n"
49
50 "loc_FFDCB5E0:\n"
51 " BL _ExitTask \n"
52 " LDMFD SP!, {R1-R5,PC} \n"
53
54 "loc_FFDCB5E8:\n"
55 " SUB R1, R1, #2 \n"
56 " CMP R1, #5 \n"
57 " ADDLS PC, PC, R1, LSL#2 \n"
58 " B loc_FFDCB5B0 \n"
59 " B loc_FFDCB610 \n"
60 " B loc_FFDCB674 \n"
61 " B loc_FFDCB67C \n"
62 " B loc_FFDCB67C \n"
63 " B loc_FFDCB67C \n"
64 " B loc_FFDCB684 \n"
65
66 "loc_FFDCB610:\n"
67 " MOV R0, #0 \n"
68 " STR R0, [SP] \n"
69
70 "loc_FFDCB618:\n"
71 " LDR R0, [R4, #0x10] \n"
72 " MOV R1, SP \n"
73 " BL sub_FFC17850 /*_GetNumberOfPostedMessages*/ \n"
74 " LDR R0, [SP] \n"
75 " CMP R0, #0 \n"
76 " BEQ loc_FFDCB644 \n"
77 " LDR R0, [R4, #0x10] \n"
78 " MOV R2, #0 \n"
79 " ADD R1, SP, #4 \n"
80 " BL sub_FFC1764C /*_ReceiveMessageQueue*/ \n"
81 " B loc_FFDCB618 \n"
82
83 "loc_FFDCB644:\n"
84 " LDR R0, [R4] \n"
85 " CMN R0, #1 \n"
86 " BEQ loc_FFDCB668 \n"
87 " BL fwt_close \n"
88 " MVN R0, #0 \n"
89 " STR R0, [R4] \n"
90 " LDR R0, =0x7ADB0 \n"
91 " BL sub_FFC3DA18 \n"
92 " BL sub_FFC3F2CC \n"
93
94 "loc_FFDCB668:\n"
95 " LDR R0, [R4, #0xC] \n"
96 " BL _GiveSemaphore \n"
97 " B loc_FFDCB5B0 \n"
98
99 "loc_FFDCB674:\n"
100 " BL sub_FFDCB848_my \n"
101 " B loc_FFDCB5B0 \n"
102
103 "loc_FFDCB67C:\n"
104 " BL sub_FFDCB988_my \n"
105 " B loc_FFDCB5B0 \n"
106
107 "loc_FFDCB684:\n"
108 " BL sub_FFDCBA84_my \n"
109 " B loc_FFDCB5B0 \n"
110 );
111 }
112
113
114
115 void __attribute__((naked,noinline)) sub_FFDCB848_my() {
116 asm volatile (
117 " STMFD SP!, {R4-R8,LR} \n"
118 " MOV R4, R0 \n"
119 " ADD R0, R0, #0x2C \n"
120 " SUB SP, SP, #0x38 \n"
121 " BL sub_FFC3DA18 \n"
122 " MOV R1, #0 \n"
123 " BL sub_FFC3F27C \n"
124 " LDR R0, [R4, #0xC] \n"
125 " BL sub_FFC3FB6C \n"
126 " LDR R7, [R4, #8] \n"
127 " LDR R8, =0x1B6 \n"
128 " ADD R6, R4, #0x2C \n"
129 " LDR R5, [R4, #0xC] \n"
130
131 " STMFD SP!, {R4-R12,LR}\n"
132 " MOV R0, R4\n"
133 " BL filewrite_main_hook\n"
134 " LDMFD SP!, {R4-R12,LR}\n"
135
136 " MOV R0, R6 \n"
137 " MOV R1, R7 \n"
138 " MOV R2, R8 \n"
139 " BL fwt_open \n"
140 " LDR PC, =0xFFDCB88C \n"
141 );
142 }
143
144
145
146 void __attribute__((naked,noinline)) sub_FFDCB988_my() {
147 asm volatile (
148 " STMFD SP!, {R4-R10,LR} \n"
149 " MOV R4, R0 \n"
150 " LDR R0, [R0] \n"
151 " CMP R0, #4 \n"
152 " LDREQ R6, [R4, #0x18] \n"
153 " LDREQ R7, [R4, #0x14] \n"
154 " BEQ loc_FFDCB9C4 \n"
155 " CMP R0, #5 \n"
156 " LDREQ R6, [R4, #0x20] \n"
157 " LDREQ R7, [R4, #0x1C] \n"
158 " BEQ loc_FFDCB9C4 \n"
159 " CMP R0, #6 \n"
160 " BNE loc_FFDCB9D8 \n"
161 " LDR R6, [R4, #0x28] \n"
162 " LDR R7, [R4, #0x24] \n"
163
164 "loc_FFDCB9C4:\n"
165 " CMP R6, #0 \n"
166 " BNE loc_FFDCB9E8 \n"
167
168 "loc_FFDCB9CC:\n"
169 " MOV R1, R4 \n"
170 " MOV R0, #7 \n"
171 " B loc_FFDCBA7C \n"
172
173 "loc_FFDCB9D8:\n"
174 " LDR R1, =0x1E2 \n"
175 " LDR R0, =0xFFDCB968 /*'dwFWrite.c'*/ \n"
176 " BL _DebugAssert \n"
177 " B loc_FFDCB9CC \n"
178
179 "loc_FFDCB9E8:\n"
180 " LDR R9, =0xAAE4 \n"
181 " MOV R5, R6 \n"
182
183 "loc_FFDCB9F0:\n"
184 " LDR R0, [R4, #4] \n"
185 " CMP R5, #0x1000000 \n"
186 " MOVLS R8, R5 \n"
187 " MOVHI R8, #0x1000000 \n"
188 " BIC R1, R0, #0xFF000000 \n"
189 " CMP R1, #0 \n"
190 " BICNE R0, R0, #0xFF000000 \n"
191 " RSBNE R0, R0, #0x1000000 \n"
192 " CMPNE R8, R0 \n"
193 " MOVHI R8, R0 \n"
194 " LDR R0, [R9] \n"
195 " MOV R2, R8 \n"
196 " MOV R1, R7 \n"
197 " BL fwt_write \n"
198 " LDR R1, [R4, #4] \n"
199 " CMP R8, R0 \n"
200 " ADD R1, R1, R0 \n"
201 " STR R1, [R4, #4] \n"
202 " BEQ loc_FFDCBA50 \n"
203 " LDR R0, =0x10B1 \n"
204 " BL sub_FFC5C534 /*_IsControlEventActive_FW*/ \n"
205 " LDR R1, =0x9200005 \n"
206 " STR R1, [R4, #0x10] \n"
207 " B loc_FFDCB9CC \n"
208
209 "loc_FFDCBA50:\n"
210 " SUB R5, R5, R0 \n"
211 " CMP R5, R6 \n"
212 " ADD R7, R7, R0 \n"
213 " LDRCS R1, =0x211 \n"
214 " LDRCS R0, =0xFFDCB968 /*'dwFWrite.c'*/ \n"
215 " BLCS _DebugAssert \n"
216 " CMP R5, #0 \n"
217 " BNE loc_FFDCB9F0 \n"
218 " LDR R0, [R4] \n"
219 " MOV R1, R4 \n"
220 " ADD R0, R0, #1 \n"
221
222 "loc_FFDCBA7C:\n"
223 " LDMFD SP!, {R4-R10,LR} \n"
224 " B sub_FFDCB500 \n"
225 );
226 }
227
228
229
230 void __attribute__((naked,noinline)) sub_FFDCBA84_my() {
231 asm volatile (
232 " STMFD SP!, {R4,R5,LR} \n"
233 " LDR R5, =0xAAE4 \n"
234 " MOV R4, R0 \n"
235 " LDR R0, [R5] \n"
236 " SUB SP, SP, #0x1C \n"
237 " CMN R0, #1 \n"
238 " BEQ sub_FFDCBAB8 \n"
239 " BL fwt_close \n"
240 " LDR PC, =0xFFDCBAA4 \n"
241 );
242 }