root/platform/a650/sub/100d/boot.c

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DEFINITIONS

This source file includes following definitions.
  1. CreateTask_spytask
  2. taskCreateHook
  3. boot
  4. sub_FFC001A4_my
  5. sub_FFC00FB8_my
  6. uHwSetup_my
  7. CreateTask_Startup_my
  8. task_Startup_my
  9. taskcreatePhySw_my
  10. init_file_modules_task
  11. sub_FFC5B788_my
  12. sub_FFC3FC8C_my
  13. sub_FFC3FAC8_my
  14. sub_FFC3F960_my

   1 /*
   2  * boot.c - auto-generated by CHDK code_gen.
   3  */
   4 #include "lolevel.h"
   5 #include "platform.h"
   6 #include "core.h"
   7 
   8 const char * const new_sa = &_end;
   9 
  10 /* Ours stuff */
  11 extern long wrs_kernel_bss_start;
  12 extern long wrs_kernel_bss_end;
  13 
  14 /*----------------------------------------------------------------------
  15     CreateTask_spytask
  16 -----------------------------------------------------------------------*/
  17 void CreateTask_spytask()
  18 {
  19     _CreateTask("SpyTask", 0x19, 0x2000, core_spytask, 0);
  20 }
  21 
  22 void taskCreateHook(int *p) {
  23     p-=16;
  24     if (p[0]==0xffc4db88)  p[0]=(int)capt_seq_task;
  25     if (p[0]==0xffc93848)  p[0]=(int)exp_drv_task;
  26     if (p[0]==0xffc4aa38)  p[0]=(int)movie_record_task;
  27     if (p[0]==0xffdce728)  p[0]=(int)filewritetask;
  28     if (p[0]==0xffc60ae8)  p[0]=(int)init_file_modules_task;
  29 }
  30 
  31 void boot()
  32 {
  33     long *canon_data_src = (void*)0xFFEAE4FC;
  34     long *canon_data_dst = (void*)0x1900;
  35     long canon_data_len = 0x12A84 - 0x1900; // data_end - data_start
  36     long *canon_bss_start = (void*)0x12A84; // just after data 
  37     long canon_bss_len = 0xA3F20 - 0x12A84; 
  38 
  39     long i;
  40 
  41 
  42     // Enable CPU caches and MPU
  43     asm volatile (
  44     "MRC     p15, 0, R0,c1,c0\n"
  45     "ORR     R0, R0, #0x1000\n"
  46     "ORR     R0, R0, #4\n"
  47     "ORR     R0, R0, #1\n"
  48     "MCR     p15, 0, R0,c1,c0\n"
  49     :::"r0");
  50 
  51     for(i=0;i<canon_data_len/4;i++)
  52     canon_data_dst[i]=canon_data_src[i];
  53 
  54     for(i=0;i<canon_bss_len/4;i++)
  55     canon_bss_start[i]=0;
  56 
  57    *(int*)0x1930=(int)taskCreateHook;
  58    *(int*)0x1934=(int)taskCreateHook;
  59 
  60     // jump to init-sequence that follows the data-copy-routine
  61     asm volatile ("B      sub_FFC001A4_my\n");
  62 };
  63 
  64 
  65 /*************************************************************/
  66 //** sub_FFC001A4_my @ 0xFFC001A4 - 0xFFC0020C, length=27
  67 void __attribute__((naked,noinline)) sub_FFC001A4_my() {
  68 asm volatile (
  69 "    LDR     R0, =0xFFC0021C \n"
  70 "    MOV     R1, #0 \n"
  71 "    LDR     R3, =0xFFC00254 \n"
  72 
  73 "loc_FFC001B0:\n"
  74 "    CMP     R0, R3 \n"
  75 "    LDRCC   R2, [R0], #4 \n"
  76 "    STRCC   R2, [R1], #4 \n"
  77 "    BCC     loc_FFC001B0 \n"
  78 "    LDR     R0, =0xFFC00254 \n"
  79 "    MOV     R1, #0x4B0 \n"
  80 "    LDR     R3, =0xFFC00468 \n"
  81 
  82 "loc_FFC001CC:\n"
  83 "    CMP     R0, R3 \n"
  84 "    LDRCC   R2, [R0], #4 \n"
  85 "    STRCC   R2, [R1], #4 \n"
  86 "    BCC     loc_FFC001CC \n"
  87 "    MOV     R0, #0xD2 \n"
  88 "    MSR     CPSR_cxsf, R0 \n"
  89 "    MOV     SP, #0x1000 \n"
  90 "    MOV     R0, #0xD3 \n"
  91 "    MSR     CPSR_cxsf, R0 \n"
  92 "    MOV     SP, #0x1000 \n"
  93 "    LDR     R0, =0x6C4 \n"
  94 "    LDR     R2, =0xEEEEEEEE \n"
  95 "    MOV     R3, #0x1000 \n"
  96 
  97 "loc_FFC00200:\n"
  98 "    CMP     R0, R3 \n"
  99 "    STRCC   R2, [R0], #4 \n"
 100 "    BCC     loc_FFC00200 \n"
 101 "    BL      sub_FFC00FB8_my \n"  // --> Patched. Old value = 0xFFC00FB8.
 102 );
 103 }
 104 
 105 /*************************************************************/
 106 //** sub_FFC00FB8_my @ 0xFFC00FB8 - 0xFFC01058, length=41
 107 void __attribute__((naked,noinline)) sub_FFC00FB8_my() {
 108 asm volatile (
 109 "    STR     LR, [SP, #-4]! \n"
 110 "    SUB     SP, SP, #0x74 \n"
 111 "    MOV     R0, SP \n"
 112 "    MOV     R1, #0x74 \n"
 113 "    BL      sub_FFE4A784 \n"
 114 "    MOV     R0, #0x53000 \n"
 115 "    STR     R0, [SP, #4] \n"
 116 
 117 #if defined(CHDK_NOT_IN_CANON_HEAP) // use original heap offset if CHDK is loaded in high memory
 118 "    LDR     R0, =0xA3F20 \n"
 119 #else
 120 "    LDR     R0, =new_sa\n"   // otherwise use patched value
 121 "    LDR     R0, [R0]\n"      //
 122 #endif
 123 
 124 "    LDR     R2, =0x2ABC00 \n"
 125 "    LDR     R1, =0x2A4968 \n"
 126 "    STR     R0, [SP, #8] \n"
 127 "    SUB     R0, R1, R0 \n"
 128 "    ADD     R3, SP, #0xC \n"
 129 "    STR     R2, [SP] \n"
 130 "    STMIA   R3, {R0-R2} \n"
 131 "    MOV     R0, #0x22 \n"
 132 "    STR     R0, [SP, #0x18] \n"
 133 "    MOV     R0, #0x68 \n"
 134 "    STR     R0, [SP, #0x1C] \n"
 135 "    LDR     R0, =0x19B \n"
 136 "    MOV     R1, #0x64 \n"
 137 "    STRD    R0, [SP, #0x20] \n"
 138 "    MOV     R0, #0x78 \n"
 139 "    STRD    R0, [SP, #0x28] \n"
 140 "    MOV     R0, #0 \n"
 141 "    STR     R0, [SP, #0x30] \n"
 142 "    STR     R0, [SP, #0x34] \n"
 143 "    MOV     R0, #0x10 \n"
 144 "    STR     R0, [SP, #0x5C] \n"
 145 "    MOV     R0, #0x800 \n"
 146 "    STR     R0, [SP, #0x60] \n"
 147 "    MOV     R0, #0xA0 \n"
 148 "    STR     R0, [SP, #0x64] \n"
 149 "    MOV     R0, #0x280 \n"
 150 "    STR     R0, [SP, #0x68] \n"
 151 "    LDR     R1, =uHwSetup_my \n"  // --> Patched. Old value = 0xFFC04DBC.
 152 "    MOV     R0, SP \n"
 153 "    MOV     R2, #0 \n"
 154 "    BL      sub_FFC02D70 \n"
 155 "    ADD     SP, SP, #0x74 \n"
 156 "    LDR     PC, [SP], #4 \n"
 157 );
 158 }
 159 
 160 /*************************************************************/
 161 //** uHwSetup_my @ 0xFFC04DBC - 0xFFC04E30, length=30
 162 void __attribute__((naked,noinline)) uHwSetup_my() {
 163 asm volatile (
 164 "    STMFD   SP!, {R4,LR} \n"
 165 "    BL      sub_FFC0095C \n"
 166 "    BL      sub_FFC09948 \n"
 167 "    CMP     R0, #0 \n"
 168 "    LDRLT   R0, =0xFFC04ED0 /*'dmSetup'*/ \n"
 169 "    BLLT    _err_init_task \n"
 170 "    BL      sub_FFC049E0 \n"
 171 "    CMP     R0, #0 \n"
 172 "    LDRLT   R0, =0xFFC04ED8 /*'termDriverInit'*/ \n"
 173 "    BLLT    _err_init_task \n"
 174 "    LDR     R0, =0xFFC04EE8 /*'/_term'*/ \n"
 175 "    BL      sub_FFC04ACC \n"
 176 "    CMP     R0, #0 \n"
 177 "    LDRLT   R0, =0xFFC04EF0 /*'termDeviceCreate'*/ \n"
 178 "    BLLT    _err_init_task \n"
 179 "    LDR     R0, =0xFFC04EE8 /*'/_term'*/ \n"
 180 "    BL      sub_FFC0357C \n"
 181 "    CMP     R0, #0 \n"
 182 "    LDRLT   R0, =0xFFC04F04 /*'stdioSetup'*/ \n"
 183 "    BLLT    _err_init_task \n"
 184 "    BL      sub_FFC094D0 \n"
 185 "    CMP     R0, #0 \n"
 186 "    LDRLT   R0, =0xFFC04F10 /*'stdlibSetup'*/ \n"
 187 "    BLLT    _err_init_task \n"
 188 "    BL      sub_FFC014D0 \n"
 189 "    CMP     R0, #0 \n"
 190 "    LDRLT   R0, =0xFFC04F1C /*'armlib_setup'*/ \n"
 191 "    BLLT    _err_init_task \n"
 192 "    LDMFD   SP!, {R4,LR} \n"
 193 "    B       CreateTask_Startup_my \n"  // --> Patched. Old value = 0xFFC0DC0C.
 194 );
 195 }
 196 
 197 /*************************************************************/
 198 //** CreateTask_Startup_my @ 0xFFC0DC0C - 0xFFC0DC74, length=27
 199 void __attribute__((naked,noinline)) CreateTask_Startup_my() {
 200 asm volatile (
 201 "    STMFD   SP!, {R3,LR} \n"
 202 //"  BL      _sub_FFC12CFC \n"  // --> Nullsub call removed.
 203 "    BL      sub_FFC1BB7C \n"
 204 "    CMP     R0, #0 \n"
 205 "    LDREQ   R0, =0xC0220000 \n"
 206 "    LDREQ   R1, [R0, #0xB8] \n"
 207 "    TSTEQ   R1, #1 \n"
 208 "    BNE     loc_FFC0DC38 \n"
 209 "    MOV     R1, #0x44 \n"
 210 "    STR     R1, [R0, #0x4C] \n"
 211 
 212 "loc_FFC0DC34:\n"
 213 "    B       loc_FFC0DC34 \n"
 214 
 215 "loc_FFC0DC38:\n"
 216 //"  BL      _sub_FFC12D04 \n"  // --> Nullsub call removed.
 217 //"  BL      _sub_FFC12D00 \n"  // --> Nullsub call removed.
 218 "    BL      sub_FFC19708 \n"
 219 "    MOV     R1, #0x300000 \n"
 220 "    MOV     R0, #0 \n"
 221 "    BL      sub_FFC19950 \n"
 222 "    BL      sub_FFC198FC \n"
 223 "    MOV     R3, #0 \n"
 224 "    STR     R3, [SP] \n"
 225 "    LDR     R3, =task_Startup_my \n"  // --> Patched. Old value = 0xFFC0DBB0.
 226 "    MOV     R2, #0 \n"
 227 "    MOV     R1, #0x19 \n"
 228 "    LDR     R0, =0xFFC0DC7C /*'Startup'*/ \n"
 229 "    BL      _CreateTask \n"
 230 "    MOV     R0, #0 \n"
 231 "    LDMFD   SP!, {R12,PC} \n"
 232 );
 233 }
 234 
 235 /*************************************************************/
 236 //** task_Startup_my @ 0xFFC0DBB0 - 0xFFC0DC04, length=22
 237 void __attribute__((naked,noinline)) task_Startup_my() {
 238 asm volatile (
 239 "    STMFD   SP!, {R4,LR} \n"
 240 "    BL      sub_FFC0517C \n"
 241 "    BL      sub_FFC13E9C \n"
 242 "    BL      sub_FFC10D98 \n"
 243 "    BL      sub_FFC37CA4 \n"
 244 "    BL      sub_FFC1BD5C \n"
 245 //"  BL      _sub_FFC1BC44 \n"  // load DISKBOOT.BIN
 246 "    BL      CreateTask_spytask\n" // added
 247 "    BL      sub_FFC5D42C \n"
 248 "    BL      sub_FFC1BDAC \n"
 249 "    BL      sub_FFC18C4C \n"
 250 "    BL      sub_FFC1BF28 \n"
 251 "    BL      taskcreatePhySw_my \n"  // --> Patched. Old value = 0xFFC12CA0. Checks buttons and acts accordingly
 252 "    BL      sub_FFC15BA4 \n"
 253 "    BL      sub_FFC1BF40 \n"
 254 //"  BL      _sub_FFC10AEC \n"  // --> Nullsub call removed.
 255 "    BL      sub_FFC12030 \n"
 256 "    BL      sub_FFC1B928 \n"
 257 "    BL      sub_FFC127CC \n"
 258 "    BL      sub_FFC11F3C \n"
 259 "    BL      sub_FFC1C888 \n"
 260 "    BL      sub_FFC11EF8 \n"
 261 "    LDMFD   SP!, {R4,LR} \n"
 262 );
 263 }
 264 
 265 /*************************************************************/
 266 //** taskcreatePhySw_my @ 0xFFC12CA0 - 0xFFC12CD4, length=14
 267 void __attribute__((naked,noinline)) taskcreatePhySw_my() {
 268 asm volatile (
 269 "    STMFD   SP!, {R3-R5,LR} \n"
 270 "    LDR     R4, =0x1C98 \n"
 271 "    LDR     R0, [R4, #0x10] \n"
 272 "    CMP     R0, #0 \n"
 273 "    BNE     loc_FFC12CD4 \n"
 274 "    MOV     R3, #0 \n"
 275 "    STR     R3, [SP] \n"
 276 "    LDR     R3, =mykbd_task \n"  // --> Patched. Old value = 0xFFC12C6C.
 277 "    MOV     R2, #0x800 \n"
 278 "    MOV     R1, #0x17 \n"
 279 "    LDR     R0, =0xFFC12E94 /*'PhySw'*/ \n"
 280 "    BL      sub_FFC0BDC8 /*_CreateTaskStrictly*/ \n"
 281 "    STR     R0, [R4, #0x10] \n"
 282 
 283 "loc_FFC12CD4:\n"
 284 "    LDMFD   SP!, {R3-R5,PC} \n"
 285 );
 286 }
 287 
 288 /*************************************************************/
 289 //** init_file_modules_task @ 0xFFC60AE8 - 0xFFC60B1C, length=14
 290 void __attribute__((naked,noinline)) init_file_modules_task() {
 291 asm volatile (
 292 "    STMFD   SP!, {R4-R6,LR} \n"
 293 "    BL      sub_FFC5B75C \n"
 294 "    LDR     R5, =0x5006 \n"
 295 "    MOVS    R4, R0 \n"
 296 "    MOVNE   R1, #0 \n"
 297 "    MOVNE   R0, R5 \n"
 298 "    BLNE    _PostLogicalEventToUI \n"
 299 "    BL      sub_FFC5B788_my \n"  // --> Patched. Old value = 0xFFC5B788.
 300 "    BL      core_spytask_can_start\n"  // CHDK: Set "it's-safe-to-start" flag for spytask
 301 "    CMP     R4, #0 \n"
 302 "    MOVEQ   R0, R5 \n"
 303 "    LDMEQFD SP!, {R4-R6,LR} \n"
 304 "    MOVEQ   R1, #0 \n"
 305 "    BEQ     _PostLogicalEventToUI \n"
 306 "    LDMFD   SP!, {R4-R6,PC} \n"
 307 );
 308 }
 309 
 310 /*************************************************************/
 311 //** sub_FFC5B788_my @ 0xFFC5B788 - 0xFFC5B7C0, length=15
 312 void __attribute__((naked,noinline)) sub_FFC5B788_my() {
 313 asm volatile (
 314 "    STMFD   SP!, {R4,LR} \n"
 315 "    BL      sub_FFC3FC8C_my \n"  // --> Patched. Old value = 0xFFC3FC8C.
 316 "    LDR     R4, =0x58B0 \n"
 317 "    LDR     R0, [R4, #4] \n"
 318 "    CMP     R0, #0 \n"
 319 "    BNE     loc_FFC5B7B8 \n"
 320 "    BL      sub_FFC69168 \n"
 321 "    BL      sub_FFCE01E8 \n"
 322 "    BL      sub_FFC69168 \n"
 323 "    BL      sub_FFCE9CC8 \n"
 324 "    BL      sub_FFC69178 \n"
 325 "    BL      sub_FFCE0288 \n"
 326 
 327 "loc_FFC5B7B8:\n"
 328 "    MOV     R0, #1 \n"
 329 "    STR     R0, [R4] \n"
 330 "    LDMFD   SP!, {R4,PC} \n"
 331 );
 332 }
 333 
 334 /*************************************************************/
 335 //** sub_FFC3FC8C_my @ 0xFFC3FC8C - 0xFFC3FD24, length=39
 336 void __attribute__((naked,noinline)) sub_FFC3FC8C_my() {
 337 asm volatile (
 338 "    STMFD   SP!, {R4-R6,LR} \n"
 339 "    MOV     R6, #0 \n"
 340 "    MOV     R0, R6 \n"
 341 "    BL      sub_FFC3F85C \n"
 342 "    LDR     R4, =0x1526C \n"
 343 "    MOV     R5, #0 \n"
 344 "    LDR     R0, [R4, #0x38] \n"
 345 "    BL      sub_FFC40224 \n"
 346 "    CMP     R0, #0 \n"
 347 "    LDREQ   R0, =0x2B7C \n"
 348 "    STREQ   R5, [R0, #0xC] \n"
 349 "    STREQ   R5, [R0, #0x10] \n"
 350 "    STREQ   R5, [R0, #0x14] \n"
 351 "    MOV     R0, R6 \n"
 352 "    BL      sub_FFC3F89C \n"
 353 "    MOV     R0, R6 \n"
 354 "    BL      sub_FFC3FAC8_my \n"  // --> Patched. Old value = 0xFFC3FAC8.
 355 "    MOV     R5, R0 \n"
 356 "    MOV     R0, R6 \n"
 357 "    BL      sub_FFC3FB34 \n"
 358 "    LDR     R1, [R4, #0x3C] \n"
 359 "    AND     R2, R5, R0 \n"
 360 "    CMP     R1, #0 \n"
 361 "    MOV     R0, #0 \n"
 362 "    MOVEQ   R0, #0x80000001 \n"
 363 "    BEQ     loc_FFC3FD20 \n"
 364 "    LDR     R3, [R4, #0x2C] \n"
 365 "    CMP     R3, #2 \n"
 366 "    MOVEQ   R0, #4 \n"
 367 "    CMP     R1, #5 \n"
 368 "    ORRNE   R0, R0, #1 \n"
 369 "    BICEQ   R0, R0, #1 \n"
 370 "    CMP     R2, #0 \n"
 371 "    BICEQ   R0, R0, #2 \n"
 372 "    ORREQ   R0, R0, #0x80000000 \n"
 373 "    BICNE   R0, R0, #0x80000000 \n"
 374 "    ORRNE   R0, R0, #2 \n"
 375 
 376 "loc_FFC3FD20:\n"
 377 "    STR     R0, [R4, #0x40] \n"
 378 "    LDMFD   SP!, {R4-R6,PC} \n"
 379 );
 380 }
 381 
 382 /*************************************************************/
 383 //** sub_FFC3FAC8_my @ 0xFFC3FAC8 - 0xFFC3FB30, length=27
 384 void __attribute__((naked,noinline)) sub_FFC3FAC8_my() {
 385 asm volatile (
 386 "    STMFD   SP!, {R4-R6,LR} \n"
 387 "    LDR     R5, =0x2B7C \n"
 388 "    MOV     R6, R0 \n"
 389 "    LDR     R0, [R5, #0x10] \n"
 390 "    CMP     R0, #0 \n"
 391 "    MOVNE   R0, #1 \n"
 392 "    LDMNEFD SP!, {R4-R6,PC} \n"
 393 "    MOV     R0, #0x17 \n"
 394 "    MUL     R1, R0, R6 \n"
 395 "    LDR     R0, =0x1526C \n"
 396 "    ADD     R4, R0, R1, LSL#2 \n"
 397 "    LDR     R0, [R4, #0x38] \n"
 398 "    MOV     R1, R6 \n"
 399 "    BL      sub_FFC3F960_my \n"  // --> Patched. Old value = 0xFFC3F960.
 400 "    CMP     R0, #0 \n"
 401 "    LDMEQFD SP!, {R4-R6,PC} \n"
 402 "    LDR     R0, [R4, #0x38] \n"
 403 "    MOV     R1, R6 \n"
 404 "    BL      sub_FFC4033C \n"
 405 "    CMP     R0, #0 \n"
 406 "    LDMEQFD SP!, {R4-R6,PC} \n"
 407 "    MOV     R0, R6 \n"
 408 "    BL      sub_FFC3F47C \n"
 409 "    CMP     R0, #0 \n"
 410 "    MOVNE   R1, #1 \n"
 411 "    STRNE   R1, [R5, #0x10] \n"
 412 "    LDMFD   SP!, {R4-R6,PC} \n"
 413 );
 414 }
 415 
 416 /*************************************************************/
 417 //** sub_FFC3F960_my @ 0xFFC3F960 - 0xFFC3FAC4, length=90
 418 void __attribute__((naked,noinline)) sub_FFC3F960_my() {
 419 asm volatile (
 420 "    STMFD   SP!, {R4-R8,LR} \n"
 421 "    MOV     R8, R0 \n"
 422 "    MOV     R0, #0x17 \n"
 423 "    MUL     R1, R0, R1 \n"
 424 "    LDR     R0, =0x1526C \n"
 425 "    MOV     R6, #0 \n"
 426 "    ADD     R7, R0, R1, LSL#2 \n"
 427 "    LDR     R0, [R7, #0x3C] \n"
 428 "    MOV     R5, #0 \n"
 429 "    CMP     R0, #6 \n"
 430 "    ADDLS   PC, PC, R0, LSL#2 \n"
 431 "    B       loc_FFC3FAAC \n"
 432 "    B       loc_FFC3F9C4 \n"
 433 "    B       loc_FFC3F9AC \n"
 434 "    B       loc_FFC3F9AC \n"
 435 "    B       loc_FFC3F9AC \n"
 436 "    B       loc_FFC3F9AC \n"
 437 "    B       loc_FFC3FAA4 \n"
 438 "    B       loc_FFC3F9AC \n"
 439 
 440 "loc_FFC3F9AC:\n"
 441 "    MOV     R2, #0 \n"
 442 "    MOV     R1, #0x200 \n"
 443 "    MOV     R0, #3 \n"
 444 "    BL      sub_FFC57C34 \n"
 445 "    MOVS    R4, R0 \n"
 446 "    BNE     loc_FFC3F9CC \n"
 447 
 448 "loc_FFC3F9C4:\n"
 449 "    MOV     R0, #0 \n"
 450 "    LDMFD   SP!, {R4-R8,PC} \n"
 451 
 452 "loc_FFC3F9CC:\n"
 453 "    LDR     R12, [R7, #0x4C] \n"
 454 "    MOV     R3, R4 \n"
 455 "    MOV     R2, #1 \n"
 456 "    MOV     R1, #0 \n"
 457 "    MOV     R0, R8 \n"
 458 "    BLX     R12 \n"
 459 "    CMP     R0, #1 \n"
 460 "    BNE     loc_FFC3F9F8 \n"
 461 "    MOV     R0, #3 \n"
 462 "    BL      sub_FFC57D74 \n"
 463 "    B       loc_FFC3F9C4 \n"
 464 
 465 "loc_FFC3F9F8:\n"
 466 "    MOV     R0, R8 \n"
 467 "    BL      sub_FFCF8D78 \n"
 468 
 469 "    MOV     R1, R4\n"              //  pointer to MBR in R1
 470 "    BL      mbr_read_dryos\n"      //  total sectors count in R0 before and after call
 471 
 472 // Start of DataGhost's FAT32 autodetection code
 473 // Policy: If there is a partition which has type W95 FAT32, use the first one of those for image storage
 474 // According to the code below, we can use R1, R2, R3 and R12.
 475 // LR wasn't really used anywhere but for storing a part of the partition signature. This is the only thing
 476 // that won't work with an offset, but since we can load from LR+offset into LR, we can use this to do that :)
 477 "    MOV     R12, R4\n"             // Copy the MBR start address so we have something to work with
 478 "    MOV     LR, R4\n"              // Save old offset for MBR signature
 479 "    MOV     R1, #1\n"              // Note the current partition number
 480 "    B       dg_sd_fat32_enter\n"   // We actually need to check the first partition as well, no increments yet!
 481 "dg_sd_fat32:\n"
 482 "    CMP     R1, #4\n"              // Did we already see the 4th partition?
 483 "    BEQ     dg_sd_fat32_end\n"     // Yes, break. We didn't find anything, so don't change anything.
 484 "    ADD     R12, R12, #0x10\n"     // Second partition
 485 "    ADD     R1, R1, #1\n"          // Second partition for the loop
 486 "dg_sd_fat32_enter:\n"
 487 "    LDRB    R2, [R12, #0x1BE]\n"   // Partition status
 488 "    LDRB    R3, [R12, #0x1C2]\n"   // Partition type (FAT32 = 0xB)
 489 "    CMP     R3, #0xB\n"            // Is this a FAT32 partition?
 490 "    CMPNE   R3, #0xC\n"            // Not 0xB, is it 0xC (FAT32 LBA) then?
 491 "    CMPNE   R3, #0x7\n"            // exFat?
 492 "    BNE     dg_sd_fat32\n"         // No, it isn't. Loop again.
 493 "    CMP     R2, #0x00\n"           // It is, check the validity of the partition type
 494 "    CMPNE   R2, #0x80\n"
 495 "    BNE     dg_sd_fat32\n"         // Invalid, go to next partition
 496                                     // This partition is valid, it's the first one, bingo!
 497 "    MOV     R4, R12\n"             // Move the new MBR offset for the partition detection.
 498 
 499 "dg_sd_fat32_end:\n"
 500 // End of DataGhost's FAT32 autodetection code
 501 
 502 "    LDRB    R1, [R4, #0x1C9] \n"
 503 "    LDRB    R3, [R4, #0x1C8] \n"
 504 "    LDRB    R12, [R4, #0x1CC] \n"
 505 "    MOV     R1, R1, LSL#24 \n"
 506 "    ORR     R1, R1, R3, LSL#16 \n"
 507 "    LDRB    R3, [R4, #0x1C7] \n"
 508 "    LDRB    R2, [R4, #0x1BE] \n"
 509 //"  LDRB    LR, [R4, #0x1FF] \n"
 510 "    ORR     R1, R1, R3, LSL#8 \n"
 511 "    LDRB    R3, [R4, #0x1C6] \n"
 512 "    CMP     R2, #0 \n"
 513 "    CMPNE   R2, #0x80 \n"
 514 "    ORR     R1, R1, R3 \n"
 515 "    LDRB    R3, [R4, #0x1CD] \n"
 516 "    MOV     R3, R3, LSL#24 \n"
 517 "    ORR     R3, R3, R12, LSL#16 \n"
 518 "    LDRB    R12, [R4, #0x1CB] \n"
 519 "    ORR     R3, R3, R12, LSL#8 \n"
 520 "    LDRB    R12, [R4, #0x1CA] \n"
 521 "    ORR     R3, R3, R12 \n"
 522 //"  LDRB    R12, [R4, #0x1FE] \n"  // Replaced, see below
 523 //mod start
 524 "    LDRB    R12, [LR,#0x1FE]\n"           // New! First MBR signature byte (0x55)
 525 "    LDRB    LR, [LR,#0x1FF]\n"            //      Last MBR signature byte (0xAA)
 526 //mod end
 527 "    MOV     R4, #0 \n"
 528 "    BNE     loc_FFC3FA80 \n"
 529 "    CMP     R0, R1 \n"
 530 "    BCC     loc_FFC3FA80 \n"
 531 "    ADD     R2, R1, R3 \n"
 532 "    CMP     R2, R0 \n"
 533 "    CMPLS   R12, #0x55 \n"
 534 "    CMPEQ   LR, #0xAA \n"
 535 "    MOVEQ   R6, R1 \n"
 536 "    MOVEQ   R5, R3 \n"
 537 "    MOVEQ   R4, #1 \n"
 538 
 539 "loc_FFC3FA80:\n"
 540 "    MOV     R0, #3 \n"
 541 "    BL      sub_FFC57D74 \n"
 542 "    CMP     R4, #0 \n"
 543 "    BNE     loc_FFC3FAB8 \n"
 544 "    MOV     R6, #0 \n"
 545 "    MOV     R0, R8 \n"
 546 "    BL      sub_FFCF8D78 \n"
 547 "    MOV     R5, R0 \n"
 548 "    B       loc_FFC3FAB8 \n"
 549 
 550 "loc_FFC3FAA4:\n"
 551 "    MOV     R5, #0x40 \n"
 552 "    B       loc_FFC3FAB8 \n"
 553 
 554 "loc_FFC3FAAC:\n"
 555 "    LDR     R1, =0x365 \n"
 556 "    LDR     R0, =0xFFC3F954 /*'Mounter.c'*/ \n"
 557 "    BL      _DebugAssert \n"
 558 
 559 "loc_FFC3FAB8:\n"
 560 "    STR     R6, [R7, #0x44]! \n"
 561 "    MOV     R0, #1 \n"
 562 "    STR     R5, [R7, #4] \n"
 563 "    LDMFD   SP!, {R4-R8,PC} \n"
 564 );
 565 }

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