This source file includes following definitions.
- taskHook
- CreateTask_spytask
- boot
- sub_FFC001A0_my
- sub_FFC00FC4_my
- uHwSetup_my
- taskcreate_Startup_my
- task_Startup_my
- taskcreatePhySw_my
- init_file_modules_task
- sub_FFC59B1C_my
- sub_FFC3E874_my
- sub_FFC3E614_my
- sub_FFC3E3A4_my
1
2
3
4 #include "lolevel.h"
5 #include "platform.h"
6 #include "core.h"
7 #include "dryos31.h"
8
9 #define offsetof(TYPE, MEMBER) ((int) &((TYPE *)0)->MEMBER)
10
11 const char * const new_sa = &_end;
12
13 extern void task_CaptSeq();
14 extern void task_InitFileModules();
15 extern void task_MovieRecord();
16 extern void task_ExpDrv();
17 extern void task_FileWrite();
18
19 void taskHook(context_t **context)
20 {
21 task_t *tcb=(task_t*)((char*)context-offsetof(task_t, context));
22
23
24 if(tcb->entry == (void*)task_CaptSeq) tcb->entry = (void*)capt_seq_task;
25 if(tcb->entry == (void*)task_InitFileModules) tcb->entry = (void*)init_file_modules_task;
26 if(tcb->entry == (void*)task_MovieRecord) tcb->entry = (void*)movie_record_task;
27 if(tcb->entry == (void*)task_ExpDrv) tcb->entry = (void*)exp_drv_task;
28 if(tcb->entry == (void*)task_FileWrite) tcb->entry = (void*)filewritetask;
29 }
30
31
32
33
34 void CreateTask_spytask() {
35 _CreateTask("SpyTask", 0x19, 0x2000, core_spytask, 0);
36 };
37
38
39
40
41
42
43
44
45
46 void __attribute__((naked,noinline)) boot() {
47 asm volatile (
48 " LDR R1, =0xC0410000 \n"
49 " MOV R0, #0 \n"
50 " STR R0, [R1] \n"
51 " MOV R1, #0x78 \n"
52 " MCR p15, 0, R1, c1, c0 \n"
53 " MOV R1, #0 \n"
54 " MCR p15, 0, R1, c7, c10, 4 \n"
55 " MCR p15, 0, R1, c7, c5 \n"
56 " MCR p15, 0, R1, c7, c6 \n"
57 " MOV R0, #0x3D \n"
58 " MCR p15, 0, R0, c6, c0 \n"
59 " MOV R0, #0xC000002F \n"
60 " MCR p15, 0, R0, c6, c1 \n"
61 " MOV R0, #0x33 \n"
62 " MCR p15, 0, R0, c6, c2 \n"
63 " MOV R0, #0x40000033 \n"
64 " MCR p15, 0, R0, c6, c3 \n"
65 " MOV R0, #0x80000017 \n"
66 " MCR p15, 0, R0, c6, c4 \n"
67 " LDR R0, =0xFFC0002B \n"
68 " MCR p15, 0, R0, c6, c5 \n"
69 " MOV R0, #0x34 \n"
70 " MCR p15, 0, R0, c2, c0 \n"
71 " MOV R0, #0x34 \n"
72 " MCR p15, 0, R0, c2, c0, 1 \n"
73 " MOV R0, #0x34 \n"
74 " MCR p15, 0, R0, c3, c0 \n"
75 " LDR R0, =0x3333330 \n"
76 " MCR p15, 0, R0, c5, c0, 2 \n"
77 " LDR R0, =0x3333330 \n"
78 " MCR p15, 0, R0, c5, c0, 3 \n"
79 " MRC p15, 0, R0, c1, c0 \n"
80 " ORR R0, R0, #0x1000 \n"
81 " ORR R0, R0, #4 \n"
82 " ORR R0, R0, #1 \n"
83 " MCR p15, 0, R0, c1, c0 \n"
84 " MOV R1, #0x80000006 \n"
85 " MCR p15, 0, R1, c9, c1 \n"
86 " MOV R1, #6 \n"
87 " MCR p15, 0, R1, c9, c1, 1 \n"
88 " MRC p15, 0, R1, c1, c0 \n"
89 " ORR R1, R1, #0x50000 \n"
90 " MCR p15, 0, R1, c1, c0 \n"
91 " LDR R2, =0xC0200000 \n"
92 " MOV R1, #1 \n"
93 " STR R1, [R2, #0x10C] \n"
94 " MOV R1, #0xFF \n"
95 " STR R1, [R2, #0xC] \n"
96 " STR R1, [R2, #0x1C] \n"
97 " STR R1, [R2, #0x2C] \n"
98 " STR R1, [R2, #0x3C] \n"
99 " STR R1, [R2, #0x4C] \n"
100 " STR R1, [R2, #0x5C] \n"
101 " STR R1, [R2, #0x6C] \n"
102 " STR R1, [R2, #0x7C] \n"
103 " STR R1, [R2, #0x8C] \n"
104 " STR R1, [R2, #0x9C] \n"
105 " STR R1, [R2, #0xAC] \n"
106 " STR R1, [R2, #0xBC] \n"
107 " STR R1, [R2, #0xCC] \n"
108 " STR R1, [R2, #0xDC] \n"
109 " STR R1, [R2, #0xEC] \n"
110 " STR R1, [R2, #0xFC] \n"
111 " LDR R1, =0xC0400008 \n"
112 " LDR R2, =0x430005 \n"
113 " STR R2, [R1] \n"
114 " MOV R1, #1 \n"
115 " LDR R2, =0xC0243100 \n"
116 " STR R2, [R1] \n"
117 " LDR R2, =0xC0242010 \n"
118 " LDR R1, [R2] \n"
119 " ORR R1, R1, #1 \n"
120 " STR R1, [R2] \n"
121 " LDR R0, =0xFFED7374 \n"
122 " LDR R1, =0x1900 \n"
123 " LDR R3, =0xB1F8 \n"
124
125 "loc_FFC0013C:\n"
126 " CMP R1, R3 \n"
127 " LDRCC R2, [R0], #4 \n"
128 " STRCC R2, [R1], #4 \n"
129 " BCC loc_FFC0013C \n"
130 " LDR R1, =0x12EDB4 \n"
131 " MOV R2, #0 \n"
132
133 "loc_FFC00154:\n"
134 " CMP R3, R1 \n"
135 " STRCC R2, [R3], #4 \n"
136 " BCC loc_FFC00154 \n"
137 " B sub_FFC001A0_my \n"
138 );
139 }
140
141
142
143 void __attribute__((naked,noinline)) sub_FFC001A0_my() {
144
145
146 *(int*)0x1930=(int)taskHook;
147 *(int*)0x1934=(int)taskHook;
148
149
150
151 *(int*)(0x2230+0x4)= (*(int*)0xC0220118) & 1 ? 0x100000 : 0x200000;
152
153 asm volatile (
154 " LDR R0, =0xFFC00218 \n"
155 " MOV R1, #0 \n"
156 " LDR R3, =0xFFC00250 \n"
157
158 "loc_FFC001AC:\n"
159 " CMP R0, R3 \n"
160 " LDRCC R2, [R0], #4 \n"
161 " STRCC R2, [R1], #4 \n"
162 " BCC loc_FFC001AC \n"
163 " LDR R0, =0xFFC00250 \n"
164 " MOV R1, #0x4B0 \n"
165 " LDR R3, =0xFFC00464 \n"
166
167 "loc_FFC001C8:\n"
168 " CMP R0, R3 \n"
169 " LDRCC R2, [R0], #4 \n"
170 " STRCC R2, [R1], #4 \n"
171 " BCC loc_FFC001C8 \n"
172 " MOV R0, #0xD2 \n"
173 " MSR CPSR_cxsf, R0 \n"
174 " MOV SP, #0x1000 \n"
175 " MOV R0, #0xD3 \n"
176 " MSR CPSR_cxsf, R0 \n"
177 " MOV SP, #0x1000 \n"
178 " LDR R0, =0x6C4 \n"
179 " LDR R2, =0xEEEEEEEE \n"
180 " MOV R3, #0x1000 \n"
181
182 "loc_FFC001FC:\n"
183 " CMP R0, R3 \n"
184 " STRCC R2, [R0], #4 \n"
185 " BCC loc_FFC001FC \n"
186 " BL sub_FFC00FC4_my \n"
187 );
188 }
189
190
191
192 void __attribute__((naked,noinline)) sub_FFC00FC4_my() {
193 asm volatile (
194 " STR LR, [SP, #-4]! \n"
195 " SUB SP, SP, #0x74 \n"
196 " MOV R0, SP \n"
197 " MOV R1, #0x74 \n"
198 " BL sub_FFE6D060 \n"
199 " MOV R0, #0x53000 \n"
200 " STR R0, [SP, #4] \n"
201
202 #if defined(CHDK_NOT_IN_CANON_HEAP)
203 " LDR R0, =0x12EDB4 \n"
204 #else
205 " LDR R0, =new_sa\n"
206 " LDR R0, [R0]\n"
207 #endif
208
209 " LDR R2, =0x2F9C00 \n"
210 " LDR R1, =0x2F24A8 \n"
211 " STR R0, [SP, #8] \n"
212 " SUB R0, R1, R0 \n"
213 " ADD R3, SP, #0xC \n"
214 " STR R2, [SP] \n"
215 " STMIA R3, {R0-R2} \n"
216 " MOV R0, #0x22 \n"
217 " STR R0, [SP, #0x18] \n"
218 " MOV R0, #0x68 \n"
219 " STR R0, [SP, #0x1C] \n"
220 " LDR R0, =0x19B \n"
221 " LDR R1, =uHwSetup_my \n"
222 " STR R0, [SP, #0x20] \n"
223 " MOV R0, #0x96 \n"
224 " STR R0, [SP, #0x24] \n"
225 " MOV R0, #0x78 \n"
226 " STR R0, [SP, #0x28] \n"
227 " MOV R0, #0x64 \n"
228 " STR R0, [SP, #0x2C] \n"
229 " MOV R0, #0 \n"
230 " STR R0, [SP, #0x30] \n"
231 " STR R0, [SP, #0x34] \n"
232 " MOV R0, #0x10 \n"
233 " STR R0, [SP, #0x5C] \n"
234 " MOV R0, #0x800 \n"
235 " STR R0, [SP, #0x60] \n"
236 " MOV R0, #0xA0 \n"
237 " STR R0, [SP, #0x64] \n"
238 " MOV R0, #0x280 \n"
239 " STR R0, [SP, #0x68] \n"
240 " MOV R0, SP \n"
241 " MOV R2, #0 \n"
242 " BL sub_FFC02D68 \n"
243 " ADD SP, SP, #0x74 \n"
244 " LDR PC, [SP], #4 \n"
245 );
246 }
247
248
249
250 void __attribute__((naked,noinline)) uHwSetup_my() {
251 asm volatile (
252 " STMFD SP!, {R4,LR} \n"
253 " BL sub_FFC00954 \n"
254 " BL sub_FFC090B4 \n"
255 " CMP R0, #0 \n"
256 " LDRLT R0, =0xFFC04E4C /*'dmSetup'*/ \n"
257 " BLLT _err_init_task \n"
258 " BL sub_FFC04974 \n"
259 " CMP R0, #0 \n"
260 " LDRLT R0, =0xFFC04E54 /*'termDriverInit'*/ \n"
261 " BLLT _err_init_task \n"
262 " LDR R0, =0xFFC04E64 /*'/_term'*/ \n"
263 " BL sub_FFC04A5C \n"
264 " CMP R0, #0 \n"
265 " LDRLT R0, =0xFFC04E6C /*'termDeviceCreate'*/ \n"
266 " BLLT _err_init_task \n"
267 " LDR R0, =0xFFC04E64 /*'/_term'*/ \n"
268 " BL sub_FFC03578 \n"
269 " CMP R0, #0 \n"
270 " LDRLT R0, =0xFFC04E80 /*'stdioSetup'*/ \n"
271 " BLLT _err_init_task \n"
272 " BL sub_FFC08BCC \n"
273 " CMP R0, #0 \n"
274 " LDRLT R0, =0xFFC04E8C /*'stdlibSetup'*/ \n"
275 " BLLT _err_init_task \n"
276 " BL sub_FFC014A8 \n"
277 " CMP R0, #0 \n"
278 " LDRLT R0, =0xFFC04E98 /*'armlib_setup'*/ \n"
279 " BLLT _err_init_task \n"
280 " LDMFD SP!, {R4,LR} \n"
281 " B taskcreate_Startup_my \n"
282 );
283 }
284
285
286
287 void __attribute__((naked,noinline)) taskcreate_Startup_my() {
288 asm volatile (
289 " STMFD SP!, {R3,LR} \n"
290
291 " BL sub_FFC186D8 \n"
292 " CMP R0, #0 \n"
293 " BNE loc_FFC0C29C \n"
294 " BL sub_FFC303F4 \n"
295 " CMP R0, #0 \n"
296 " BNE loc_FFC0C29C \n"
297 " BL sub_FFC10E84 \n"
298 " LDR R1, =0xC0220000 \n"
299 " MOV R0, #0x44 \n"
300 " STR R0, [R1, #0x84] \n"
301 " STR R0, [R1, #0x80] \n"
302 " BL sub_FFC11074 \n"
303
304 "loc_FFC0C298:\n"
305 " B loc_FFC0C298 \n"
306
307 "loc_FFC0C29C:\n"
308
309
310 " BL sub_FFC16994 \n"
311 " LDR R1, =0x34E000 \n"
312 " MOV R0, #0 \n"
313 " BL sub_FFC16DDC \n"
314 " BL sub_FFC16B88 /*_EnableDispatch*/ \n"
315 " MOV R3, #0 \n"
316 " STR R3, [SP] \n"
317 " LDR R3, =task_Startup_my \n"
318 " MOV R2, #0 \n"
319 " MOV R1, #0x19 \n"
320 " LDR R0, =0xFFC0C2E4 /*'Startup'*/ \n"
321 " BL _CreateTask \n"
322 " MOV R0, #0 \n"
323 " LDMFD SP!, {R12,PC} \n"
324 );
325 }
326
327
328
329 void __attribute__((naked,noinline)) task_Startup_my() {
330 asm volatile (
331 " STMFD SP!, {R4,LR} \n"
332 " BL sub_FFC05394 \n"
333 " BL sub_FFC128A0 \n"
334 " BL sub_FFC10B28 \n"
335
336 " BL sub_FFC188FC \n"
337
338 " BL sub_FFC5CD74 \n"
339 " BL sub_FFC0FB94 \n"
340 " BL sub_FFC1892C \n"
341 " BL sub_FFC15F94 \n"
342 " BL sub_FFC18A9C \n"
343 " BL CreateTask_spytask\n"
344 " BL taskcreatePhySw_my \n"
345
346 #if defined(OPT_RUN_WITH_BATT_COVER_OPEN)
347 " LDR R0, =0xE0000\n"
348 "batt_delay:\n"
349 " NOP\n"
350 " SUBS R0,R0,#1\n"
351 " BNE batt_delay\n"
352 #endif
353
354 " BL sub_FFC146C0 \n"
355 " BL sub_FFC18AB4 \n"
356
357 " BL sub_FFC104B0 \n"
358 " BL sub_FFC184BC \n"
359 " BL sub_FFC10AD8 \n"
360 " BL sub_FFC103D4 \n"
361 " BL sub_FFC0FBC8 \n"
362 " BL sub_FFC194FC \n"
363 " BL sub_FFC103AC \n"
364 " LDMFD SP!, {R4,LR} \n"
365 " B sub_FFC054B4 \n"
366 );
367 }
368
369
370
371 void __attribute__((naked,noinline)) taskcreatePhySw_my() {
372 asm volatile (
373 " STMFD SP!, {R3-R5,LR} \n"
374 " LDR R4, =0x1C18 \n"
375 " LDR R0, [R4, #0x10] \n"
376 " CMP R0, #0 \n"
377 " BNE sub_FFC116E4 \n"
378 " MOV R3, #0 \n"
379 " STR R3, [SP] \n"
380 " LDR R3, =mykbd_task \n"
381 " MOV R2, #0x2000 \n"
382 " LDR PC, =0xFFC116D4 \n"
383 );
384 }
385
386
387
388 void __attribute__((naked,noinline)) init_file_modules_task() {
389 asm volatile (
390 " STMFD SP!, {R4-R6,LR} \n"
391 " BL sub_FFC59AF0 \n"
392 " LDR R5, =0x5006 \n"
393 " MOVS R4, R0 \n"
394 " MOVNE R1, #0 \n"
395 " MOVNE R0, R5 \n"
396 " BLNE _PostLogicalEventToUI \n"
397 " BL sub_FFC59B1C_my \n"
398 " BL core_spytask_can_start\n"
399 " CMP R4, #0 \n"
400 " MOVEQ R0, R5 \n"
401 " LDMEQFD SP!, {R4-R6,LR} \n"
402 " MOVEQ R1, #0 \n"
403 " BEQ _PostLogicalEventToUI \n"
404 " LDMFD SP!, {R4-R6,PC} \n"
405 );
406 }
407
408
409
410 void __attribute__((naked,noinline)) sub_FFC59B1C_my() {
411 asm volatile (
412 " STMFD SP!, {R4,LR} \n"
413 " MOV R0, #3 \n"
414 " BL sub_FFC3E874_my \n"
415 " LDR PC, =0xFFC59B28 \n"
416 );
417 }
418
419
420
421 void __attribute__((naked,noinline)) sub_FFC3E874_my() {
422 asm volatile (
423 " STMFD SP!, {R4-R8,LR} \n"
424 " MOV R6, R0 \n"
425 " BL sub_FFC3E7DC \n"
426 " LDR R1, =0xE618 \n"
427 " MOV R5, R0 \n"
428 " ADD R4, R1, R0, LSL#7 \n"
429 " LDR R0, [R4, #0x70] \n"
430 " CMP R0, #4 \n"
431 " LDREQ R1, =0x6D8 \n"
432 " LDREQ R0, =0xFFC3E300 /*'Mounter.c'*/ \n"
433 " BLEQ _DebugAssert \n"
434 " MOV R1, R6 \n"
435 " MOV R0, R5 \n"
436 " BL sub_FFC3E248 \n"
437 " LDR R0, [R4, #0x38] \n"
438 " BL sub_FFC3EDA0 \n"
439 " CMP R0, #0 \n"
440 " STREQ R0, [R4, #0x70] \n"
441 " MOV R0, R5 \n"
442 " BL sub_FFC3E320 \n"
443 " MOV R0, R5 \n"
444 " BL sub_FFC3E614_my \n"
445 " LDR PC, =0xFFC3E8CC \n"
446 );
447 }
448
449
450
451 void __attribute__((naked,noinline)) sub_FFC3E614_my() {
452 asm volatile (
453 " STMFD SP!, {R4-R6,LR} \n"
454 " MOV R5, R0 \n"
455 " LDR R0, =0xE618 \n"
456 " ADD R4, R0, R5, LSL#7 \n"
457 " LDR R0, [R4, #0x70] \n"
458 " TST R0, #2 \n"
459 " MOVNE R0, #1 \n"
460 " LDMNEFD SP!, {R4-R6,PC} \n"
461 " LDR R0, [R4, #0x38] \n"
462 " MOV R1, R5 \n"
463 " BL sub_FFC3E3A4_my \n"
464 " LDR PC, =0xFFC3E640 \n"
465 );
466 }
467
468
469
470 void __attribute__((naked,noinline)) sub_FFC3E3A4_my() {
471 asm volatile (
472 " STMFD SP!, {R4-R8,LR} \n"
473 " MOV R8, R0 \n"
474 " LDR R0, =0xE618 \n"
475 " MOV R7, #0 \n"
476 " ADD R5, R0, R1, LSL#7 \n"
477 " LDR R0, [R5, #0x3C] \n"
478 " MOV R6, #0 \n"
479 " CMP R0, #7 \n"
480 " ADDLS PC, PC, R0, LSL#2 \n"
481 " B loc_FFC3E4F4 \n"
482 " B loc_FFC3E404 \n"
483 " B loc_FFC3E3EC \n"
484 " B loc_FFC3E3EC \n"
485 " B loc_FFC3E3EC \n"
486 " B loc_FFC3E3EC \n"
487 " B loc_FFC3E4EC \n"
488 " B loc_FFC3E3EC \n"
489 " B loc_FFC3E3EC \n"
490
491 "loc_FFC3E3EC:\n"
492 " MOV R2, #0 \n"
493 " MOV R1, #0x200 \n"
494 " MOV R0, #2 \n"
495 " BL _exmem_ualloc \n"
496 " MOVS R4, R0 \n"
497 " BNE loc_FFC3E40C \n"
498
499 "loc_FFC3E404:\n"
500 " MOV R0, #0 \n"
501 " LDMFD SP!, {R4-R8,PC} \n"
502
503 "loc_FFC3E40C:\n"
504 " LDR R12, [R5, #0x4C] \n"
505 " MOV R3, R4 \n"
506 " MOV R2, #1 \n"
507 " MOV R1, #0 \n"
508 " MOV R0, R8 \n"
509 " BLX R12 \n"
510 " CMP R0, #1 \n"
511 " BNE loc_FFC3E438 \n"
512 " MOV R0, #2 \n"
513 " BL _exmem_ufree \n"
514 " B loc_FFC3E404 \n"
515
516 "loc_FFC3E438:\n"
517 " LDR R1, [R5, #0x68] \n"
518 " MOV R0, R8 \n"
519 " BLX R1 \n"
520
521 " MOV R1, R4\n"
522 " BL mbr_read_dryos\n"
523
524
525
526
527
528
529 " MOV R12, R4\n"
530 " MOV LR, R4\n"
531 " MOV R1, #1\n"
532 " B dg_sd_fat32_enter\n"
533 "dg_sd_fat32:\n"
534 " CMP R1, #4\n"
535 " BEQ dg_sd_fat32_end\n"
536 " ADD R12, R12, #0x10\n"
537 " ADD R1, R1, #1\n"
538 "dg_sd_fat32_enter:\n"
539 " LDRB R2, [R12, #0x1BE]\n"
540 " LDRB R3, [R12, #0x1C2]\n"
541 " CMP R3, #0xB\n"
542 " CMPNE R3, #0xC\n"
543 " CMPNE R3, #0x7\n"
544 " BNE dg_sd_fat32\n"
545 " CMP R2, #0x00\n"
546 " CMPNE R2, #0x80\n"
547 " BNE dg_sd_fat32\n"
548
549 " MOV R4, R12\n"
550
551 "dg_sd_fat32_end:\n"
552
553
554 " LDRB R1, [R4, #0x1C9] \n"
555 " LDRB R3, [R4, #0x1C8] \n"
556 " LDRB R12, [R4, #0x1CC] \n"
557 " MOV R1, R1, LSL#24 \n"
558 " ORR R1, R1, R3, LSL#16 \n"
559 " LDRB R3, [R4, #0x1C7] \n"
560 " LDRB R2, [R4, #0x1BE] \n"
561
562 " ORR R1, R1, R3, LSL#8 \n"
563 " LDRB R3, [R4, #0x1C6] \n"
564 " CMP R2, #0 \n"
565 " CMPNE R2, #0x80 \n"
566 " ORR R1, R1, R3 \n"
567 " LDRB R3, [R4, #0x1CD] \n"
568 " MOV R3, R3, LSL#24 \n"
569 " ORR R3, R3, R12, LSL#16 \n"
570 " LDRB R12, [R4, #0x1CB] \n"
571 " ORR R3, R3, R12, LSL#8 \n"
572 " LDRB R12, [R4, #0x1CA] \n"
573 " ORR R3, R3, R12 \n"
574
575
576 " LDRB R12, [LR,#0x1FE]\n"
577 " LDRB LR, [LR,#0x1FF]\n"
578
579 " MOV R4, #0 \n"
580 " BNE loc_FFC3E4C4 \n"
581 " CMP R0, R1 \n"
582 " BCC loc_FFC3E4C4 \n"
583 " ADD R2, R1, R3 \n"
584 " CMP R2, R0 \n"
585 " CMPLS R12, #0x55 \n"
586 " CMPEQ LR, #0xAA \n"
587 " MOVEQ R7, R1 \n"
588 " MOVEQ R6, R3 \n"
589 " MOVEQ R4, #1 \n"
590
591 "loc_FFC3E4C4:\n"
592 " MOV R0, #2 \n"
593 " BL _exmem_ufree \n"
594 " CMP R4, #0 \n"
595 " BNE loc_FFC3E500 \n"
596 " LDR R1, [R5, #0x68] \n"
597 " MOV R7, #0 \n"
598 " MOV R0, R8 \n"
599 " BLX R1 \n"
600 " MOV R6, R0 \n"
601 " B loc_FFC3E500 \n"
602
603 "loc_FFC3E4EC:\n"
604 " MOV R6, #0x40 \n"
605 " B loc_FFC3E500 \n"
606
607 "loc_FFC3E4F4:\n"
608 " LDR R1, =0x5C9 \n"
609 " LDR R0, =0xFFC3E300 /*'Mounter.c'*/ \n"
610 " BL _DebugAssert \n"
611
612 "loc_FFC3E500:\n"
613 " STR R7, [R5, #0x44]! \n"
614 " MOV R0, #1 \n"
615 " STR R6, [R5, #4] \n"
616 " LDMFD SP!, {R4-R8,PC} \n"
617 );
618 }