This source file includes following definitions.
- filewritetask
- sub_FF32E53C_my
- sub_FF32EB7C_my
- sub_FF32E6A8_my
1
2
3
4 #include "lolevel.h"
5 #include "platform.h"
6
7 typedef struct {
8 unsigned int address;
9 unsigned int length;
10 } cam_ptp_data_chunk;
11
12 #define MAX_CHUNKS_FOR_FWT 7
13
14
15
16
17
18
19
20 typedef struct
21 {
22 int unkn1;
23 int file_offset;
24 int full_size;
25 int unkn2, unkn3, unkn4;
26 cam_ptp_data_chunk pdc[MAX_CHUNKS_FOR_FWT];
27 int seek_flag;
28 char name[32];
29
30 } fwt_data_struct;
31 #define FWT_MUSTSEEK 2
32 #define FWT_SEEKMASK 0xffffffff
33
34 #include "../../../generic/filewrite.c"
35
36
37
38 void __attribute__((naked,noinline)) filewritetask() {
39 asm volatile (
40 " STMFD SP!, {R1-R7,LR} \n"
41 " LDR R7, =0xF1A4 \n"
42 " MOV R6, #0 \n"
43
44 "loc_FF32E84C:\n"
45 " LDR R0, [R7, #0x14] \n"
46 " MOV R2, #0 \n"
47 " ADD R1, SP, #8 \n"
48 " MOV R5, R7 \n"
49 " BL sub_0068BBE4 /*_ReceiveMessageQueue*/ \n"
50 " CMP R0, #0 \n"
51 " LDRNE R1, =0x38E \n"
52 " LDRNE R0, =0xFF32E984 /*'dwFWrite.c'*/ \n"
53 " BLNE _DebugAssert \n"
54 " LDR R0, [SP, #8] \n"
55 " LDR R1, [R0] \n"
56 " CMP R1, #0xB \n"
57 " ADDCC PC, PC, R1, LSL#2 \n"
58 " B loc_FF32E84C \n"
59 " B loc_FF32E954 \n"
60 " B loc_FF32E954 \n"
61 " B loc_FF32E954 \n"
62 " B loc_FF32E954 \n"
63 " B loc_FF32E954 \n"
64 " B loc_FF32E954 \n"
65 " B loc_FF32E954 \n"
66 " B loc_FF32E95C \n"
67 " B loc_FF32E8B0 \n"
68 " B loc_FF32E920 \n"
69 " B loc_FF32E918 \n"
70
71 "loc_FF32E8B0:\n"
72 " STR R6, [SP] \n"
73
74 "loc_FF32E8B4:\n"
75 " LDR R0, [R5, #0x14] \n"
76 " MOV R1, SP \n"
77 " BL sub_0068BE28 /*_GetNumberOfPostedMessages*/ \n"
78 " LDR R0, [SP] \n"
79 " CMP R0, #0 \n"
80 " BEQ loc_FF32E8E0 \n"
81 " LDR R0, [R5, #0x14] \n"
82 " MOV R2, #0 \n"
83 " ADD R1, SP, #4 \n"
84 " BL sub_0068BBE4 /*_ReceiveMessageQueue*/ \n"
85 " B loc_FF32E8B4 \n"
86
87 "loc_FF32E8E0:\n"
88 " LDR R0, [R5, #8] \n"
89 " CMN R0, #1 \n"
90 " BEQ loc_FF32E90C \n"
91 " BL fwt_close \n"
92 " MVN R0, #0 \n"
93 " STR R0, [R5, #8] \n"
94 " LDR R0, =0x16C2C8 \n"
95 " STR R6, [R5, #4] \n"
96 " BL sub_FF060B08 \n"
97 " MOV R1, #0 \n"
98 " BL sub_FF05ED80 \n"
99
100 "loc_FF32E90C:\n"
101 " LDR R0, [R5, #0x10] \n"
102 " BL _GiveSemaphore \n"
103 " B loc_FF32E84C \n"
104
105 "loc_FF32E918:\n"
106 " BL sub_FF32E53C_my \n"
107 " B loc_FF32E84C \n"
108
109 "loc_FF32E920:\n"
110 " LDR R1, [R0, #4] \n"
111 " MOV R4, R0 \n"
112 " LDR R0, [R5, #8] \n"
113 " MOV R2, #0 \n"
114 " BL fwt_lseek \n"
115 " CMN R0, #1 \n"
116 " LDREQ R0, =0x9200013 \n"
117 " MOV R1, R4 \n"
118 " STREQ R0, [R4, #0x14] \n"
119 " MOVNE R0, #0 \n"
120 " MOVEQ R0, #7 \n"
121 " BL sub_FF32E480 \n"
122 " B loc_FF32E84C \n"
123
124 "loc_FF32E954:\n"
125 " BL sub_FF32EB7C_my \n"
126 " B loc_FF32E84C \n"
127
128 "loc_FF32E95C:\n"
129 " BL sub_FF32E6A8_my \n"
130 " B loc_FF32E84C \n"
131 );
132 }
133
134
135
136 void __attribute__((naked,noinline)) sub_FF32E53C_my() {
137 asm volatile (
138 " STMFD SP!, {R4-R9,LR} \n"
139 " LDR R6, =0xF1A4 \n"
140 " MOV R4, R0 \n"
141
142
143 " STMFD SP!, {R4-R12,LR}\n"
144 " BL filewrite_main_hook\n"
145 " LDMFD SP!, {R4-R12,LR}\n"
146
147 " LDR R0, [R6, #4] \n"
148 " SUB SP, SP, #0x3C \n"
149 " CMP R0, #0 \n"
150 " BNE loc_FF32E678 \n"
151 " ADD R0, R4, #0x54 \n"
152 " BL sub_FF060B08 \n"
153 " MOV R1, #0 \n"
154 " BL sub_FF05EC44 \n"
155 " LDR R0, [R4, #0x10] \n"
156 " BL sub_FF000370 \n"
157 " LDR R0, [R4, #0x50] \n"
158 " LDR R9, =0x1B6 \n"
159 " CMP R0, #1 \n"
160 " LDREQ R0, [R4, #0xC] \n"
161 " ADD R7, R4, #0x54 \n"
162 " ORREQ R0, R0, #0x8000 \n"
163 " STREQ R0, [R4, #0xC] \n"
164 " LDR R8, [R4, #0xC] \n"
165 " LDR R5, [R4, #0x10] \n"
166 " MOV R2, R9 \n"
167 " MOV R1, R8 \n"
168 " MOV R0, R7 \n"
169 " BL fwt_open \n"
170 " CMN R0, #1 \n"
171 " BNE loc_FF32E608 \n"
172 " MOV R0, R7 \n"
173 " BL sub_FF02233C \n"
174 " MOV R2, #0xF \n"
175 " MOV R1, R7 \n"
176 " ADD R0, SP, #4 \n"
177 " BL sub_0069017C \n"
178 " MOV R0, #0 \n"
179 " LDR R1, =0x41FF \n"
180 " STRB R0, [SP, #0x13] \n"
181 " STR R1, [SP, #0x24] \n"
182 " MOV R1, #0x10 \n"
183 " STR R0, [SP, #0x2C] \n"
184 " STR R1, [SP, #0x28] \n"
185 " ADD R1, SP, #0x24 \n"
186 " ADD R0, SP, #4 \n"
187 " STR R5, [SP, #0x30] \n"
188 " STR R5, [SP, #0x34] \n"
189 " STR R5, [SP, #0x38] \n"
190 " BL sub_FF05E5C0 \n"
191 " MOV R2, R9 \n"
192 " MOV R1, R8 \n"
193 " MOV R0, R7 \n"
194 " BL _Open \n"
195
196 "loc_FF32E608:\n"
197 " CMN R0, #1 \n"
198 " MOV R5, R0 \n"
199 " STR R0, [R6, #8] \n"
200 " BNE loc_FF32E644 \n"
201 " ADD R0, R4, #0x54 \n"
202 " BL sub_FF060B08 \n"
203 " LDR R1, [R6, #0x1C] \n"
204 " BL sub_FF05ED80 \n"
205 " LDR R1, [R6, #0x18] \n"
206 " CMP R1, #0 \n"
207 " BEQ loc_FF32E6A0 \n"
208 " ADD SP, SP, #0x3C \n"
209 " LDMFD SP!, {R4-R9,LR} \n"
210 " LDR R0, =0x9200001 \n"
211 " BX R1 \n"
212
213 "loc_FF32E644:\n"
214 " MOV R0, #1 \n"
215 " STR R0, [R6, #4] \n"
216 " LDR R0, =0x16C2C8 \n"
217 " MOV R2, #0x20 \n"
218 " ADD R1, R4, #0x54 \n"
219 " BL sub_00690364 \n"
220
221 " LDR R3, =current_write_ignored\n"
222 " LDR R3, [R3]\n"
223 " CMP R3, #0\n"
224 " BNE loc_A\n"
225
226 " LDR R1, [R4, #8] \n"
227 " MOV R0, R5 \n"
228 " BL sub_FF02200C \n"
229 " CMP R0, #0 \n"
230 " MOVEQ R1, R4 \n"
231 " MOVEQ R0, #7 \n"
232 " BEQ loc_FF32E69C \n"
233
234 "loc_FF32E678:\n"
235 "loc_A:\n"
236 " LDR R0, [R4, #0x50] \n"
237 " CMP R0, #2 \n"
238 " BEQ loc_FF32E694 \n"
239 " LDR R0, [R4, #4] \n"
240 " CMP R0, #0 \n"
241 " MOVEQ R1, R4 \n"
242 " BEQ loc_FF32E69C \n"
243
244 "loc_FF32E694:\n"
245 " MOV R1, R4 \n"
246 " MOV R0, #9 \n"
247
248 "loc_FF32E69C:\n"
249 " BL sub_FF32E480 \n"
250
251 "loc_FF32E6A0:\n"
252 " ADD SP, SP, #0x3C \n"
253 " LDMFD SP!, {R4-R9,PC} \n"
254 );
255 }
256
257
258
259 void __attribute__((naked,noinline)) sub_FF32EB7C_my() {
260 asm volatile (
261 " STMFD SP!, {R4-R10,LR} \n"
262 " MOV R5, R0 \n"
263 " LDR R0, [R0] \n"
264 " CMP R0, #6 \n"
265 " BHI loc_FF32EBA8 \n"
266 " ADD R0, R5, R0, LSL#3 \n"
267 " LDR R8, [R0, #0x18]! \n"
268 " LDR R7, [R0, #4] \n"
269 " CMP R7, #0 \n"
270 " BNE loc_FF32EBC0 \n"
271 " B loc_FF32EBB4 \n"
272
273 "loc_FF32EBA8:\n"
274 " LDR R1, =0x2DD \n"
275 " LDR R0, =0xFF32E984 /*'dwFWrite.c'*/ \n"
276 " BL _DebugAssert \n"
277
278 "loc_FF32EBB4:\n"
279 " MOV R1, R5 \n"
280 " MOV R0, #7 \n"
281 " B loc_FF32EC54 \n"
282
283 "loc_FF32EBC0:\n"
284 " LDR R9, =0xF1A4 \n"
285 " MOV R4, R7 \n"
286
287 "loc_FF32EBC8:\n"
288 " LDR R0, [R5, #4] \n"
289 " CMP R4, #0x1000000 \n"
290 " MOVLS R6, R4 \n"
291 " MOVHI R6, #0x1000000 \n"
292 " BIC R1, R0, #0xFF000000 \n"
293 " CMP R1, #0 \n"
294 " BICNE R0, R0, #0xFF000000 \n"
295 " RSBNE R0, R0, #0x1000000 \n"
296 " CMPNE R6, R0 \n"
297 " MOVHI R6, R0 \n"
298 " LDR R0, [R9, #8] \n"
299 " MOV R2, R6 \n"
300 " MOV R1, R8 \n"
301 " BL fwt_write \n"
302 " LDR R1, [R5, #4] \n"
303 " CMP R6, R0 \n"
304 " ADD R1, R1, R0 \n"
305 " STR R1, [R5, #4] \n"
306 " BEQ loc_FF32EC28 \n"
307 " CMN R0, #1 \n"
308 " LDRNE R0, =0x9200015 \n"
309 " LDREQ R0, =0x9200005 \n"
310 " STR R0, [R5, #0x14] \n"
311 " B loc_FF32EBB4 \n"
312
313 "loc_FF32EC28:\n"
314 " SUB R4, R4, R0 \n"
315 " CMP R4, R7 \n"
316 " ADD R8, R8, R0 \n"
317 " MOVCS R1, #0x308 \n"
318 " LDRCS R0, =0xFF32E984 /*'dwFWrite.c'*/ \n"
319 " BLCS _DebugAssert \n"
320 " CMP R4, #0 \n"
321 " BNE loc_FF32EBC8 \n"
322 " LDR R0, [R5] \n"
323 " MOV R1, R5 \n"
324 " ADD R0, R0, #1 \n"
325
326 "loc_FF32EC54:\n"
327 " LDMFD SP!, {R4-R10,LR} \n"
328 " B sub_FF32E480 \n"
329 );
330 }
331
332
333
334 void __attribute__((naked,noinline)) sub_FF32E6A8_my() {
335 asm volatile (
336 " STMFD SP!, {R4-R6,LR} \n"
337 " MOV R4, R0 \n"
338 " LDR R0, [R0, #0x50] \n"
339 " LDR R5, =0xF1A4 \n"
340 " CMP R0, #3 \n"
341 " SUB SP, SP, #0x38 \n"
342 " BEQ loc_FF32E820 \n"
343 " LDR R0, [R5, #8] \n"
344 " CMN R0, #1 \n"
345 " BEQ loc_FF32E6FC \n"
346 " LDR R1, [R4, #0xC] \n"
347 " LDR R6, =0x9200003 \n"
348 " TST R1, #0x8000 \n"
349 " BEQ loc_FF32E6E8 \n"
350
351 " LDR R3, =current_write_ignored\n"
352 " LDR R3, [R3]\n"
353 " CMP R3, #0\n"
354 " BNE loc_B\n"
355
356 " BL sub_FF021D60 \n"
357 " B loc_FF32E6EC \n"
358
359 "loc_FF32E6E8:\n"
360 "loc_B:\n"
361 " BL fwt_close \n"
362
363 "loc_FF32E6EC:\n"
364 " CMP R0, #0 \n"
365 " MVN R0, #0 \n"
366 " STRNE R6, [R4, #0x14] \n"
367 " STR R0, [R5, #8] \n"
368
369 "loc_FF32E6FC:\n"
370 " LDR R0, [R4, #0x14] \n"
371 " TST R0, #1 \n"
372 " BNE loc_FF32E804 \n"
373 " LDR R0, [R4, #0xC] \n"
374 " TST R0, #8 \n"
375 " BNE loc_FF32E720 \n"
376 " LDR R0, [R4, #0x50] \n"
377 " CMP R0, #3 \n"
378 " BNE loc_FF32E750 \n"
379
380 "loc_FF32E720:\n"
381 " ADD R1, SP, #0x20 \n"
382 " ADD R0, R4, #0x54 \n"
383 " BL sub_FF05E508 \n"
384 " CMP R0, #0 \n"
385 " LDREQ R1, =0x346 \n"
386 " LDREQ R0, =0xFF32E984 /*'dwFWrite.c'*/ \n"
387 " BLEQ _DebugAssert \n"
388 " LDR R0, [SP, #0x28] \n"
389 " LDR R1, [R4, #4] \n"
390 " ADD R0, R0, R1 \n"
391 " STR R0, [SP, #0x28] \n"
392 " B loc_FF32E780 \n"
393
394 "loc_FF32E750:\n"
395 " LDR R0, =0x81FF \n"
396 " STR R0, [SP, #0x20] \n"
397 " MOV R0, #0x20 \n"
398 " STR R0, [SP, #0x24] \n"
399 " LDR R0, [R4, #4] \n"
400 " STR R0, [SP, #0x28] \n"
401 " LDR R0, [R4, #0x10] \n"
402 " STR R0, [SP, #0x2C] \n"
403 " LDR R0, [R4, #0x10] \n"
404 " STR R0, [SP, #0x30] \n"
405 " LDR R0, [R4, #0x10] \n"
406 " STR R0, [SP, #0x34] \n"
407
408 "loc_FF32E780:\n"
409 " LDR R0, [R4, #0x50] \n"
410 " CMP R0, #2 \n"
411 " BEQ loc_FF32E804 \n"
412 " ADD R1, SP, #0x20 \n"
413 " ADD R0, R4, #0x54 \n"
414 " BL sub_FF05E5C0 \n"
415 " LDR R0, [R4, #0x50] \n"
416 " CMP R0, #1 \n"
417 " BNE loc_FF32E804 \n"
418 " MOV R2, #0x20 \n"
419 " ADD R1, R4, #0x54 \n"
420 " MOV R0, SP \n"
421 " BL sub_00690364 \n"
422 " MOV R0, SP \n"
423 " BL _strlen \n"
424 " MOV R2, #0x54 \n"
425 " ADD R0, R0, SP \n"
426 " MOV R1, #0x4D \n"
427 " STRB R2, [R0, #-3] \n"
428 " STRB R1, [R0, #-2] \n"
429 " MOV R1, #0x50 \n"
430 " STRB R1, [R0, #-1] \n"
431 " MOV R1, SP \n"
432 " ADD R0, R4, #0x54 \n"
433 " BL sub_FF05DE58 \n"
434 " CMP R0, #0 \n"
435 " MOVEQ R1, #0x164 \n"
436 " LDREQ R0, =0xFF32E984 /*'dwFWrite.c'*/ \n"
437 " BLEQ _DebugAssert \n"
438 " MOV R0, SP \n"
439 " BL sub_FF05EA1C \n"
440 " ADD R0, R4, #0x54 \n"
441 " BL sub_FF05EA1C \n"
442
443 "loc_FF32E804:\n"
444 " ADD R0, R4, #0x54 \n"
445 " BL sub_FF060B08 \n"
446 " LDR R1, [R5, #0x1C] \n"
447 " BL sub_FF05ED80 \n"
448 " MOV R0, #0 \n"
449 " STR R0, [R5, #4] \n"
450 " B loc_FF32E828 \n"
451
452 "loc_FF32E820:\n"
453 " LDR R0, [R5, #0x1C] \n"
454 " BLX R0 \n"
455
456 "loc_FF32E828:\n"
457 " LDR R1, [R5, #0x18] \n"
458 " CMP R1, #0 \n"
459 " LDRNE R0, [R4, #0x14] \n"
460 " BLXNE R1 \n"
461 " ADD SP, SP, #0x38 \n"
462 " LDMFD SP!, {R4-R6,PC} \n"
463 );
464 }