root/platform/ixus130_sd1400/sub/100a/boot.c

DEFINITIONS

1. taskHook
2. CreateTask_spytask
3. boot
4. sub_FF810354_my
5. sub_FF811198_my
6. sub_FF815E58_my
7. taskcreate_Startup_my
8. taskcreate_PhySw_my
9. task_Startup_my
10. init_file_modules_task
11. sub_FF88CAEC_my
12. sub_FF86F084_my
13. sub_FF86ECAC_my
14. sub_FF86E9CC_my

   1 #include "lolevel.h"
   2 #include "platform.h"
   3 #include "core.h"
   4 #include "dryos31.h"
   6 #define offsetof(TYPE, MEMBER) ((int) &((TYPE *)0)->MEMBER)
   8 const char * const new_sa = &_end;
  10 extern void task_PhySw();
  11 extern void task_CaptSeq();
  12 extern void task_InitFileModules();
  13 extern void task_RotaryEncoder();
  14 extern void task_MovieRecord();
  15 extern void task_ExpDrv();
  16 extern void task_FileWrite();
  18 void taskHook(context_t **context)
  19 {
task_t *tcb=(task_t*)((char*)context-offsetof(task_t, context));
  21         // Replace firmware task addresses with ours
  22         if(tcb->entry == (void*)task_PhySw)             tcb->entry = (void*)mykbd_task;
  23         if(tcb->entry == (void*)task_CaptSeq)                   tcb->entry = (void*)capt_seq_task;
  24         if(tcb->entry == (void*)task_InitFileModules)   tcb->entry = (void*)init_file_modules_task;
  25         if(tcb->entry == (void*)task_MovieRecord)               tcb->entry = (void*)movie_record_task;
  26         if(tcb->entry == (void*)task_ExpDrv)                    tcb->entry = (void*)exp_drv_task;
  27     if(tcb->entry == (void*)task_FileWrite)         tcb->entry = (void*)filewritetask;
  28 }
  30 void CreateTask_spytask() {
_CreateTask("SpyTask", 0x19, 0x2000, core_spytask, 0);
  32 };
  34 void __attribute__((naked,noinline)) boot(  ) {
  35 asm volatile (
  36 "    LDR     R1, =0xC0410000 \n"
  37 "    MOV     R0, #0 \n"
  38 "    STR     R0, [R1] \n"
  39 "    MOV     R1, #0x78 \n"
  40 "    MCR     p15, 0, R1, c1, c0 \n"
  41 "    MOV     R1, #0 \n"
  42 "    MCR     p15, 0, R1, c7, c10, 4 \n"
  43 "    MCR     p15, 0, R1, c7, c5 \n"
  44 "    MCR     p15, 0, R1, c7, c6 \n"
  45 "    MOV     R0, #0x3D \n"
  46 "    MCR     p15, 0, R0, c6, c0 \n"
  47 "    MOV     R0, #0xC000002F \n"
  48 "    MCR     p15, 0, R0, c6, c1 \n"
  49 "    MOV     R0, #0x33 \n"
  50 "    MCR     p15, 0, R0, c6, c2 \n"
  51 "    MOV     R0, #0x40000033 \n"
  52 "    MCR     p15, 0, R0, c6, c3 \n"
  53 "    MOV     R0, #0x80000017 \n"
  54 "    MCR     p15, 0, R0, c6, c4 \n"
  55 "    LDR     R0, =0xFF80002D \n"
  56 "    MCR     p15, 0, R0, c6, c5 \n"
  57 "    MOV     R0, #0x34 \n"
  58 "    MCR     p15, 0, R0, c2, c0 \n"
  59 "    MOV     R0, #0x34 \n"
  60 "    MCR     p15, 0, R0, c2, c0, 1 \n"
  61 "    MOV     R0, #0x34 \n"
  62 "    MCR     p15, 0, R0, c3, c0 \n"
  63 "    LDR     R0, =0x3333330 \n"
  64 "    MCR     p15, 0, R0, c5, c0, 2 \n"
  65 "    LDR     R0, =0x3333330 \n"
  66 "    MCR     p15, 0, R0, c5, c0, 3 \n"
  67 "    MRC     p15, 0, R0, c1, c0 \n"
  68 "    ORR     R0, R0, #0x1000 \n"
  69 "    ORR     R0, R0, #4 \n"
  70 "    ORR     R0, R0, #1 \n"
  71 "    MCR     p15, 0, R0, c1, c0 \n"
  72 "    MOV     R1, #0x80000006 \n"
  73 "    MCR     p15, 0, R1, c9, c1 \n"
  74 "    MOV     R1, #6 \n"
  75 "    MCR     p15, 0, R1, c9, c1, 1 \n"
  76 "    MRC     p15, 0, R1, c1, c0 \n"
  77 "    ORR     R1, R1, #0x50000 \n"
  78 "    MCR     p15, 0, R1, c1, c0 \n"
  79 "    LDR     R2, =0xC0200000 \n"
  80 "    MOV     R1, #1 \n"
  81 "    STR     R1, [R2, #0x10C] \n"
  82 "    MOV     R1, #0xFF \n"
  83 "    STR     R1, [R2, #0xC] \n"
  84 "    STR     R1, [R2, #0x1C] \n"
  85 "    STR     R1, [R2, #0x2C] \n"
  86 "    STR     R1, [R2, #0x3C] \n"
  87 "    STR     R1, [R2, #0x4C] \n"
  88 "    STR     R1, [R2, #0x5C] \n"
  89 "    STR     R1, [R2, #0x6C] \n"
  90 "    STR     R1, [R2, #0x7C] \n"
  91 "    STR     R1, [R2, #0x8C] \n"
  92 "    STR     R1, [R2, #0x9C] \n"
  93 "    STR     R1, [R2, #0xAC] \n"
  94 "    STR     R1, [R2, #0xBC] \n"
  95 "    STR     R1, [R2, #0xCC] \n"
  96 "    STR     R1, [R2, #0xDC] \n"
  97 "    STR     R1, [R2, #0xEC] \n"
  98 "    STR     R1, [R2, #0xFC] \n"
  99 "    LDR     R1, =0xC0400008 \n"
 100 "    LDR     R2, =0x430005 \n"
 101 "    STR     R2, [R1] \n"
 102 "    MOV     R1, #1 \n"
 103 "    LDR     R2, =0xC0243100 \n"
 104 "    STR     R2, [R1] \n"
 105 "    LDR     R2, =0xC0242010 \n"
 106 "    LDR     R1, [R2] \n"
 107 "    ORR     R1, R1, #1 \n"
 108 "    STR     R1, [R2] \n"
 109 "    LDR     R0, =0xFFBF837C \n"   // 1.00a
 110 "    LDR     R1, =0x1900 \n"
 111 "    LDR     R3, =0xEBD0 \n"
 112 "loc_FF81013C:\n"
 113 "    CMP     R1, R3 \n"
 114 "    LDRCC   R2, [R0], #4 \n"
 115 "    STRCC   R2, [R1], #4 \n"
 116 "    BCC     loc_FF81013C \n"
 117 "    LDR     R1, =0x14FE20 \n"
 118 "    MOV     R2, #0 \n"
 119 "loc_FF810154:\n"
 120 "    CMP     R3, R1 \n"
 121 "    STRCC   R2, [R3], #4 \n"
 122 "    BCC     loc_FF810154 \n"
 123 "    B       sub_FF810354_my \n" //--------->
 124         );
 125 };
 128 void __attribute__((naked,noinline)) sub_FF810354_my(  ) {
 130   // Power Button detection (short press = playback mode, long press = record mode)
 131   // replacement for sub_ff834348
 132   *(int*)0x2480 = (*(int*)0xC0220128) & 1 ? 0x400000 : 0x200000;
 134   *(int*)0x1938 = (int)taskHook;
 136 asm volatile (
 137 "    LDR     R0, =0xFF8103CC \n"
 138 "    MOV     R1, #0 \n"
 139 "    LDR     R3, =0xFF810404 \n"
 140 "loc_FF810360:\n"
 141 "    CMP     R0, R3 \n"
 142 "    LDRCC   R2, [R0], #4 \n"
 143 "    STRCC   R2, [R1], #4 \n"
 144 "    BCC     loc_FF810360 \n"
 145 "    LDR     R0, =0xFF810404 \n"
 146 "    MOV     R1, #0x4B0 \n"
 147 "    LDR     R3, =0xFF810618 \n"
 148 "loc_FF81037C:\n"
 149 "    CMP     R0, R3 \n"
 150 "    LDRCC   R2, [R0], #4 \n"
 151 "    STRCC   R2, [R1], #4 \n"
 152 "    BCC     loc_FF81037C \n"
 153 "    MOV     R0, #0xD2 \n"
 154 "    MSR     CPSR_cxsf, R0 \n"
 155 "    MOV     SP, #0x1000 \n"
 156 "    MOV     R0, #0xD3 \n"
 157 "    MSR     CPSR_cxsf, R0 \n"
 158 "    MOV     SP, #0x1000 \n"
 159 "    LDR     R0, =0x6C4 \n"
 160 "    LDR     R2, =0xEEEEEEEE \n"
 161 "    MOV     R3, #0x1000 \n"
 162 "loc_FF8103B0:\n"
 163 "    CMP     R0, R3 \n"
 164 "    STRCC   R2, [R0], #4 \n"
 165 "    BCC     loc_FF8103B0 \n"
 166 "    BL      sub_FF811198_my \n"  //-------------->
 167         );
 168 }
 170 void __attribute__((naked,noinline)) sub_FF811198_my(  ) {
 171 asm volatile (
 172 "    STR     LR, [SP, #-4]! \n"
 173 "    SUB     SP, SP, #0x74 \n"
 174 "    MOV     R0, SP \n"
 175 "    MOV     R1, #0x74 \n"
 176 "    BL      sub_FFB39910 \n"    // 1.00a
 177 "    MOV     R0, #0x53000 \n"
 178 "    STR     R0, [SP, #4] \n"
 180 #if defined(CHDK_NOT_IN_CANON_HEAP) // use original heap offset if CHDK is loaded in high memory
 181 "    LDR     R0, =0x14FE20 \n"
 182 #else
 183 "    LDR     R0, =new_sa\n"        // otherwise use patched value
 184 "    LDR     R0, [R0]\n"           // 
 185 #endif
 187 "    LDR     R2, =0x339C00\n"
 188 "    LDR     R1, =0x3324A8\n"
 189 "    STR     R0, [SP, #8] \n"
 190 "    SUB     R0, R1, R0 \n"
 191 "    ADD     R3, SP, #0xC \n"
 192 "    STR     R2, [SP] \n"
 193 "    STMIA   R3, {R0-R2} \n"
 194 "    MOV     R0, #0x22 \n"
 195 "    STR     R0, [SP, #0x18] \n"
 196 "    MOV     R0, #0x68 \n"
 197 "    STR     R0, [SP, #0x1C] \n"
 198 "    LDR     R0, =0x19B \n"
 199 "    LDR     R1, =sub_FF815E58_my \n" //---------->
 200 "    STR     R0, [SP, #0x20] \n"
 201 "    MOV     R0, #0x96 \n"
 202 "    STR     R0, [SP, #0x24] \n"
 203 "    MOV     R0, #0x78 \n"
 204 "    STR     R0, [SP, #0x28] \n"
 205 "    MOV     R0, #0x64 \n"
 206 "    STR     R0, [SP, #0x2C] \n"
 207 "    MOV     R0, #0 \n"
 208 "    STR     R0, [SP, #0x30] \n"
 209 "    STR     R0, [SP, #0x34] \n"
 210 "    MOV     R0, #0x10 \n"
 211 "    STR     R0, [SP, #0x5C] \n"
 212 "    MOV     R0, #0x800 \n"
 213 "    STR     R0, [SP, #0x60] \n"
 214 "    MOV     R0, #0xA0 \n"
 215 "    STR     R0, [SP, #0x64] \n"
 216 "    MOV     R0, #0x280 \n"
 217 "    STR     R0, [SP, #0x68] \n"
 218 "    MOV     R0, SP \n"
 219 "    MOV     R2, #0 \n"
 220 "    BL      sub_FF813404 \n"
 221 "    ADD     SP, SP, #0x74 \n"
 222 "    LDR     PC, [SP], #4 \n"
 223         );
 224 }
 227 void __attribute__((naked,noinline)) sub_FF815E58_my(  ) {
 228 asm volatile (
 229 "    STMFD   SP!, {R4,LR} \n"
 230 "    BL      sub_FF810B20 \n"
 231 "    BL      sub_FF81A244 \n"
 232 "    CMP     R0, #0 \n"
 233 "    LDRLT   R0, =0xFF815F6C \n"
 234 "    BLLT    sub_FF815F4C \n"
 235 "    BL      sub_FF815A94 \n"
 236 "    CMP     R0, #0 \n"
 237 "    LDRLT   R0, =0xFF815F74 \n"
 238 "    BLLT    sub_FF815F4C \n"
 239 "    LDR     R0, =0xFF815F84 \n"
 240 "    BL      sub_FF815B7C \n"
 241 "    CMP     R0, #0 \n"
 242 "    LDRLT   R0, =0xFF815F8C \n"
 243 "    BLLT    sub_FF815F4C \n"
 244 "    LDR     R0, =0xFF815F84 \n"
 245 "    BL      sub_FF813BF0 \n"
 246 "    CMP     R0, #0 \n"
 247 "    LDRLT   R0, =0xFF815FA0 \n"
 248 "    BLLT    sub_FF815F4C \n"
 249 "    BL      sub_FF819C3C \n"
 250 "    CMP     R0, #0 \n"
 251 "    LDRLT   R0, =0xFF815FAC \n"
 252 "    BLLT    sub_FF815F4C \n"
 253 "    BL      sub_FF81167C \n"
 254 "    CMP     R0, #0 \n"
 255 "    LDRLT   R0, =0xFF815FB8 \n"
 256 "    BLLT    sub_FF815F4C \n"
 257 "    LDMFD   SP!, {R4,LR} \n"
 258 "    B       taskcreate_Startup_my\n" //-------->
 259         );
 260 }
 263 void __attribute__((naked,noinline)) taskcreate_Startup_my(  ) {
 264 asm volatile (
 265 "    STMFD   SP!, {R3,LR}\n"
 266 "    BL      sub_FF834340\n"
 267 "    BL      sub_FF83BA88\n"
 268 "    CMP     R0, #0\n"
 269 "    BNE     loc_FF81FB34 \n"
 270 "    BL      sub_FF835B2C \n"
 271 "    CMP     R0, #0 \n"
 272 "    BEQ     loc_FF81FB34 \n"
 273 "    BL      sub_FF83433C \n"
 274 "    CMP     R0, #0 \n"
 275 "    BNE     loc_FF81FB34 \n"
 276 "    BL      sub_FF8339DC \n"
 277 "    LDR     R1, =0xC0220000 \n"
 278 "    MOV     R0, #0x44 \n"
 279 "    STR     R0, [R1, #0x1C] \n"
 280 "    BL      sub_FF833BC8 \n"
 281 "loc_FF81FB30:\n"
 282 "    B       loc_FF81FB30 \n"
 283 "loc_FF81FB34:\n"
 284 //"    BL      sub_FF834348 \n"   // hijack power-on
 285 "    BL      sub_FF834344 \n"
 286 "    BL      sub_FF839CB0 \n"
 287 "    LDR     R1, =0x38E000 \n"
 288 "    MOV     R0, #0 \n"
 289 "    BL      sub_FF83A0F8 \n"
 290 "    BL      sub_FF839EA4 \n"
 291 "    MOV     R3, #0 \n"
 292 "    STR     R3, [SP] \n"
 293 "    LDR     R3, =task_Startup_my \n"   //------->
 294 "    MOV     R2, #0 \n"
 295 "    MOV     R1, #0x19 \n"
 296 "    LDR     R0, =0xFF81FB7C \n"
 297 "    BL      sub_FF81E83C \n"
 298 "    MOV     R0, #0 \n"
 299 "    LDMFD   SP!, {R12,PC} \n"
 300    );
 301 }
 303 void __attribute__((naked,noinline)) taskcreate_PhySw_my() {
 304 asm volatile(
 305 "    STMFD   SP!, {R3-R5,LR} \n"
 306 "    LDR     R4, =0x1C20 \n"
 307 "    LDR     R0, [R4, #0x10] \n"
 308 "    CMP     R0, #0 \n"
 309 "    BNE     loc_FF834264 \n"
 310 "    MOV     R3, #0 \n"
 311 "    STR     R3, [SP] \n"
 312 "    LDR     R3,  =mykbd_task\n"                // Changed
 313 //"  MOV     R2, #0x800 \n"
 314 "    MOV     R2, #0x2000\n"                     // + stack size for new task_PhySw so we don't have to do stack switch
 315 "    B       sub_FF834254\n"   //  continue in code
 316 "loc_FF834264:\n"
 317 "    BL      sub_FF834264 \n"    // continue in code
 318         );
 319 }
 321 void __attribute__((naked,noinline)) task_Startup_my(  ) {
 322 asm volatile (
 323 "    STMFD   SP!, {R4,LR} \n"
 324 "    BL      sub_FF81650C \n"
 325 "    BL      sub_FF83543C \n"
 326 "    BL      sub_FF833638 \n"
 327 "    BL      sub_FF83BAC8 \n"
 328 "    BL      sub_FF83BCB4 \n"
 329 //"    BL      sub_FF83BB5C \n" // This should be the DISKBOOT start
 330 "    BL      sub_FF83BE58 \n"
 331 "    BL      sub_FF8322E4 \n"
 332 "    BL      sub_FF83BCE4 \n"
 333 "    BL      sub_FF839454 \n"
 334 "    BL      CreateTask_spytask\n" // +
 335 "    BL      sub_FF83BE5C \n"
 336 //"  BL      sub_FF834230 \n"
 337 "    BL      taskcreate_PhySw_my\n"     // +
 338 "    BL      sub_FF8377A8 \n"
 339 "    BL      sub_FF83BE74 \n"
 340 "    BL      sub_FF8316A8 \n"
 341 "    BL      sub_FF833090 \n"
 342 "    BL      sub_FF83B860 \n"
 343 "    BL      sub_FF8335EC \n"
 344 "    BL      sub_FF83302C \n"
 345 "    BL      sub_FF832318 \n"
 346 "    BL      sub_FF83C8F4 \n"
 347 "    BL      sub_FF833004 \n"
 348 "    LDMFD   SP!, {R4,LR} \n"
 349 "    B       sub_FF81662C \n"
 350      );
 351 }
 353 /*----------------------------------------------------------------------
 354         init_file_modules_task()
 355 -----------------------------------------------------------------------*/
 356 void __attribute__((naked,noinline)) init_file_modules_task(  ) {
 357 asm volatile (
 358 "    STMFD   SP!, {R4-R6,LR} \n"
 359 "    BL      sub_FF88CAC0 \n"    // 1.00a
 360 "    LDR     R5, =0x5006 \n"
 361 "    MOVS    R4, R0 \n"
 362 "    MOVNE   R1, #0 \n"
 363 "    MOVNE   R0, R5 \n"
 364 "    BLNE    sub_FF8904CC \n"     // 1.00a
 365 "    BL      sub_FF88CAEC_my \n"  // 1.00a  ----->
 366 "    BL      core_spytask_can_start\n"  // added
 367 "    CMP     R4, #0 \n"
 368 "    MOVEQ   R0, R5 \n"
 369 "    LDMEQFD SP!, {R4-R6,LR} \n"
 370 "    MOVEQ   R1, #0 \n"
 371 "    BEQ     sub_FF8904CC \n"     // 1.00a
 372 "    LDMFD   SP!, {R4-R6,PC} \n"
 373         );
 374 }
 377 void __attribute__((naked,noinline)) sub_FF88CAEC_my() {
 378 asm volatile (
 379 "    STMFD   SP!, {R4,LR} \n"
 380 "    MOV     R0, #3 \n"
 381 "    BL      sub_FF86F084_my \n"    //----->
 382 "    BL      sub_FF93FFDC \n"     //  1.00a
 383 "    LDR     R4, =0x2F54 \n"
 384 "    LDR     R0, [R4, #4] \n"
 385 "    CMP     R0, #0 \n"
 386 "    BNE     loc_FF88CB24 \n"    // 1.00a
 387 "    BL      sub_FF86E2CC \n"
 388 "    BL      sub_FF9344A0 \n"    // 1.00a
 389 "    BL      sub_FF86E2CC \n"
 390 "    BL      sub_FF86A6F0 \n"
 391 "    BL      sub_FF86E1CC \n"
 392 "    BL      sub_FF93453C \n"    // 1.00a
 393 "loc_FF88CB24:\n"                // 1.00a     
 394 "    MOV     R0, #1 \n"
 395 "    STR     R0, [R4] \n"
 396 "    LDMFD   SP!, {R4,PC} \n"
 397         );
 398 }
 401 void __attribute__((naked,noinline)) sub_FF86F084_my(  ) {
 402 asm volatile (
 403 "    STMFD   SP!, {R4-R8,LR} \n"
 404 "    MOV     R8, R0 \n"
 405 "    BL      sub_FF86F004 \n"
 406 "    LDR     R1, =0x38448 \n"
 407 "    MOV     R6, R0 \n"
 408 "    ADD     R4, R1, R0, LSL #7 \n"
 409 "    LDR     R0, [R4, #0x6C] \n"
 410 "    CMP     R0, #4 \n"
 411 "    LDREQ   R1, =0x85A \n"
 412 "    LDREQ   R0, =0xFF86EB44 \n"
 413 "    BLEQ    sub_FF81EB14 \n"
 414 "    MOV     R1, R8 \n"
 415 "    MOV     R0, R6 \n"
 416 "    BL      sub_FF86E8BC \n"
 417 "    LDR     R0, [R4, #0x38] \n"
 418 "    BL      sub_FF86F724 \n"
 419 "    CMP     R0, #0 \n"
 420 "    STREQ   R0, [R4, #0x6C] \n"
 421 "    MOV     R0, R6 \n"
 422 "    BL      sub_FF86E94C \n"      
 423 "    MOV     R0, R6 \n"
 424 "    BL      sub_FF86ECAC_my \n"    //  ----->
 425 "    MOV     R5, R0 \n"
 426 "    MOV     R0, R6 \n"
 427 "    BL      sub_FF86EEDC \n"
 428 "    LDR     R6, [R4, #0x3C] \n"
 429 "    AND     R7, R5, R0 \n"
 430 "    CMP     R6, #0 \n"
 431 "    LDR     R1, [R4, #0x38] \n"
 432 "    MOVEQ   R0, #0x80000001 \n"
 433 "    MOV     R5, #0 \n"
 434 "    BEQ     loc_FF86F134 \n"
 435 "    MOV     R0, R1 \n"
 436 "    BL      sub_FF86E434 \n"
 437 "    CMP     R0, #0 \n"
 438 "    MOVNE   R5, #4 \n"
 439 "    CMP     R6, #5 \n"
 440 "    ORRNE   R0, R5, #1 \n"
 441 "    BICEQ   R0, R5, #1 \n"
 442 "    CMP     R7, #0 \n"
 443 "    BICEQ   R0, R0, #2 \n"
 444 "    ORREQ   R0, R0, #0x80000000 \n"
 445 "    BICNE   R0, R0, #0x80000000 \n"
 446 "    ORRNE   R0, R0, #2 \n"
 447 "loc_FF86F134:\n"
 448 "    CMP     R8, #7 \n"
 449 "    STR     R0, [R4, #0x40] \n"
 450 "    LDMNEFD SP!, {R4-R8,PC} \n"
 451 "    MOV     R0, R8 \n"
 452 "    BL      sub_FF86F054 \n"
 453 "    CMP     R0, #0 \n"
 454 "    LDMEQFD SP!, {R4-R8,LR} \n"
 455 "    LDREQ   R0, =0xFF86F180 \n"
 456 "    BEQ     sub_FF81177C \n"
 457 "    LDMFD   SP!, {R4-R8,PC} \n"
 458         );
 459 }
 461 void __attribute__((naked,noinline)) sub_FF86ECAC_my(  ) {
 462 asm volatile (
 463 "    STMFD   SP!, {R4-R6,LR} \n"
 464 "    MOV     R5, R0 \n"
 465 "    LDR     R0, =0x38448 \n"
 466 "    ADD     R4, R0, R5, LSL #7 \n"
 467 "    LDR     R0, [R4, #0x6C] \n"
 468 "    TST     R0, #2 \n"
 469 "    MOVNE   R0, #1 \n"
 470 "    LDMNEFD SP!, {R4-R6,PC} \n"
 471 "    LDR     R0, [R4, #0x38] \n"
 472 "    MOV     R1, R5 \n"
 473 "    BL      sub_FF86E9CC_my \n"     // ------>
 474 "    CMP     R0, #0 \n"
 475 "    LDRNE   R0, [R4, #0x38] \n"
 476 "    MOVNE   R1, R5 \n"
 477 "    BLNE    sub_FF86EB68 \n"
 478 "    LDR     R2, =0x384C8 \n"
 479 "    ADD     R1, R5, R5, LSL #4 \n"
 480 "    LDR     R1, [R2, R1, LSL #2] \n"
 481 "    CMP     R1, #4 \n"
 482 "    BEQ     loc_FF86ED0C \n"
 483 "    CMP     R0, #0 \n"
 484 "    LDMEQFD SP!, {R4-R6,PC} \n"
 485 "    MOV     R0, R5 \n"
 486 "    BL      sub_FF86E4C4 \n"
 487 "loc_FF86ED0C:\n"
 488 "    CMP     R0, #0 \n"
 489 "    LDRNE   R1, [R4, #0x6C] \n"
 490 "    ORRNE   R1, R1, #2 \n"
 491 "    STRNE   R1, [R4, #0x6C] \n"
 492 "    LDMFD   SP!, {R4-R6,PC} \n"
 493         );
 494 }
 497 void __attribute__((naked,noinline)) sub_FF86E9CC_my(  ) {
 498 asm volatile (
 499 "    STMFD   SP!, {R4-R10,LR} \n"
 500 "    MOV     R9, R0 \n"
 501 "    LDR     R0, =0x38448 \n"
 502 "    MOV     R8, #0 \n"
 503 "    ADD     R5, R0, R1, LSL #7 \n"
 504 "    LDR     R0, [R5, #0x3C] \n"
 505 "    MOV     R7, #0 \n"
 506 "    CMP     R0, #7 \n"
 507 "    MOV     R6, #0 \n"
 508 "    ADDLS   PC, PC, R0, LSL #2 \n"
 509 "    B       loc_FF86EB24 \n"
 510 "    B       loc_FF86EA30 \n"
 511 "    B       loc_FF86EA18 \n"
 512 "    B       loc_FF86EA18 \n"
 513 "    B       loc_FF86EA18 \n"
 514 "    B       loc_FF86EA18 \n"
 515 "    B       loc_FF86EB1C \n"
 516 "    B       loc_FF86EA18 \n"
 517 "    B       loc_FF86EA18 \n"
 518 "loc_FF86EA18:\n"
 519 "    MOV     R2, #0 \n"
 520 "    MOV     R1, #0x200 \n"
 521 "    MOV     R0, #2 \n"
 522 "    BL      sub_FF886B70 \n"   // 1.00a
 523 "    MOVS    R4, R0 \n"
 524 "    BNE     loc_FF86EA38 \n"
 525 "loc_FF86EA30:\n"
 526 "    MOV     R0, #0 \n"
 527 "    LDMFD   SP!, {R4-R10,PC} \n"
 528 "loc_FF86EA38:\n"
 529 "    LDR     R12, [R5, #0x50] \n"
 530 "    MOV     R3, R4 \n"
 531 "    MOV     R2, #1 \n"
 532 "    MOV     R1, #0 \n"
 533 "    MOV     R0, R9 \n"
 534 "    BLX     R12 \n"
 535 "    CMP     R0, #1 \n"
 536 "    BNE     loc_FF86EA64 \n"
 537 "    MOV     R0, #2 \n"
 538 "    BL      sub_FF886CBC \n"    // 1.00a
 539 "    B       loc_FF86EA30 \n"
 540 "loc_FF86EA64:\n"
 541 "    LDR     R1, [R5, #0x64] \n"
 542 "    MOV     R0, R9 \n"
 543 "    BLX     R1 \n"
 545 //------------------  begin added code ---------------
 546                 "MOV   R1, R4\n"           //  pointer to MBR in R1
 547                 "BL    mbr_read_dryos\n"   //  total sectors count in R0 before and after call
 549                 // Start of DataGhost's FAT32 autodetection code
 550                 // Policy: If there is a partition which has type W95 FAT32, use the first one of those for image storage
 551                 // According to the code below, we can use R1, R2, R3 and R12.
 552                 // LR wasn't really used anywhere but for storing a part of the partition signature. This is the only thing
 553                 // that won't work with an offset, but since we can load from LR+offset into LR, we can use this to do that :)
 554                 "MOV     R12, R4\n"                    // Copy the MBR start address so we have something to work with
 555                 "MOV     LR, R4\n"                     // Save old offset for MBR signature
 556                 "MOV     R1, #1\n"                     // Note the current partition number
 557                 "B       dg_sd_fat32_enter\n"          // We actually need to check the first partition as well, no increments yet!
 558    "dg_sd_fat32:\n"
 559                 "CMP     R1, #4\n"                     // Did we already see the 4th partition?
 560                 "BEQ     dg_sd_fat32_end\n"            // Yes, break. We didn't find anything, so don't change anything.
 561                 "ADD     R12, R12, #0x10\n"            // Second partition
 562                 "ADD     R1, R1, #1\n"                 // Second partition for the loop
 563    "dg_sd_fat32_enter:\n"
 564                 "LDRB    R2, [R12, #0x1BE]\n"          // Partition status
 565                 "LDRB    R3, [R12, #0x1C2]\n"          // Partition type (FAT32 = 0xB)
 566                 "CMP     R3, #0xB\n"                   // Is this a FAT32 partition?
 567                 "CMPNE   R3, #0xC\n"                   // Not 0xB, is it 0xC (FAT32 LBA) then?
 568                 "BNE     dg_sd_fat32\n"                // No, it isn't.
 569                 "CMP     R2, #0x00\n"                  // It is, check the validity of the partition type
 570                 "CMPNE   R2, #0x80\n"
 571                 "BNE     dg_sd_fat32\n"                // Invalid, go to next partition
 572                                                                                            // This partition is valid, it's the first one, bingo!
 573                 "MOV     R4, R12\n"                    // Move the new MBR offset for the partition detection.
 575    "dg_sd_fat32_end:\n"
 576                 // End of DataGhost's FAT32 autodetection code
 577 //------------------  end added code ---------------
 580 "    LDRB    R1, [R4, #0x1C9] \n"
 581 "    LDRB    R3, [R4, #0x1C8] \n"
 582 "    LDRB    R12, [R4, #0x1CC] \n"
 583 "    MOV     R1, R1, LSL #0x18 \n"
 584 "    ORR     R1, R1, R3, LSL #0x10 \n"
 585 "    LDRB    R3, [R4, #0x1C7] \n"
 586 "    LDRB    R2, [R4, #0x1BE] \n"
 588 //"    LDRB    LR, [R4, #0x1FF] \n" // delete for FAT32
 590 "    ORR     R1, R1, R3, LSL #8 \n"
 591 "    LDRB    R3, [R4, #0x1C6] \n"
 592 "    CMP     R2, #0 \n"
 593 "    CMPNE   R2, #0x80 \n"
 594 "    ORR     R1, R1, R3 \n"
 595 "    LDRB    R3, [R4, #0x1CD] \n"
 596 "    MOV     R3, R3, LSL #0x18 \n"
 597 "    ORR     R3, R3, R12, LSL #0x10 \n"
 598 "    LDRB    R12, [R4, #0x1CB] \n"
 599 "    ORR     R3, R3, R12, LSL #8 \n"
 600 "    LDRB    R12, [R4, #0x1CA] \n"
 601 "    ORR     R3, R3, R12 \n"
 603 //"    LDRB    R12, [R4, #0x1FE] \n"    // delete for FAT32
 604 "    LDRB    R12, [LR,#0x1FE]\n"        // New! First MBR signature byte (0x55)
 605 "    LDRB    LR, [LR,#0x1FF]\n"         //      Last MBR signature byte (0xAA)
 607 "    BNE     loc_FF86EAF0 \n"
 608 "    CMP     R0, R1 \n"
 609 "    BCC     loc_FF86EAF0 \n"
 610 "    ADD     R2, R1, R3 \n"
 611 "    CMP     R2, R0 \n"
 612 "    CMPLS   R12, #0x55 \n"
 613 "    CMPEQ   LR, #0xAA \n"
 614 "    MOVEQ   R7, R1 \n"
 615 "    MOVEQ   R6, R3 \n"
 616 "    MOVEQ   R4, #1 \n"
 617 "    BEQ     loc_FF86EAF4 \n"
 618 "loc_FF86EAF0:\n"
 619 "    MOV     R4, R8 \n"
 620 "loc_FF86EAF4:\n"
 621 "    MOV     R0, #2 \n"
 622 "    BL      sub_FF886CBC \n"   // 1.00a
 623 "    CMP     R4, #0 \n"
 624 "    BNE     loc_FF86EB30 \n"
 625 "    LDR     R1, [R5, #0x64] \n"
 626 "    MOV     R7, #0 \n"
 627 "    MOV     R0, R9 \n"
 628 "    BLX     R1 \n"
 629 "    MOV     R6, R0 \n"
 630 "    B       loc_FF86EB30 \n"
 631 "loc_FF86EB1C:\n"
 632 "    MOV     R6, #0x40 \n"
 633 "    B       loc_FF86EB30 \n"
 634 "loc_FF86EB24:\n"
 635 "    LDR     R1, =0x5B2 \n"
 636 "    LDR     R0, =0xFF86EB44 \n"
 637 "    BL      sub_FF81EB14 \n"
 638 "loc_FF86EB30:\n"
 639 "    STR     R7, [R5, #0x44]! \n"
 640 "    STMIB   R5, {R6,R8} \n"
 641 "    MOV     R0, #1 \n"
 642 "    LDMFD   SP!, {R4-R10,PC} \n"
 643         );
 644 }