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cpuinfo_v7.c-Dateireferenz

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Datenstrukturen

struct  mmuregs_s
 
struct  l1tblentry_s
 

Funktionen

static const char * two_on_nth (unsigned val)
 
static const char * two_on_nth_granule (unsigned val)
 
static const char * mmfr3_cache (unsigned val)
 
static const char * mmfr3_bp (unsigned val)
 
static const char * mmfr3_cms (unsigned val)
 
static const char * mmfr3_ss (unsigned val)
 
static const char * ctype_str (unsigned val)
 
static const char * ccsidr_linesize (unsigned val)
 
static const char * ccsidr_plusone (unsigned val)
 
static const char * cache_tcm_size_str (unsigned val)
 
static const char * cache_tcm_addr_str (unsigned val)
 
static const char * mpu_region_size_str (unsigned val)
 
static const char * bitfield8 (unsigned val)
 
static const char * mpu_rattr (unsigned val)
 
static const char * dbg_version (unsigned val)
 
void __attribute__ ((naked, noinline))
 
static const char * tlb_unified (unsigned val)
 
static const char * tlb_entries (unsigned val)
 
static const char * ttbraddr0 (unsigned val)
 
static const char * ttbraddr1 (unsigned val)
 
static const char * ttbcr_n (unsigned val)
 
unsigned interpret_l1_table_entry (unsigned e, char *buf)
 
unsigned interpret_l2_table_entry (unsigned e, char *buf)
 
void memmapping_vmsa (FILE *f)
 

Variablen

static char linebuf [256]
 
static const char * two_nth_str []
 
struct cpuinfo_bitfield_desc_s cpuinf_feat0 []
 
struct cpuinfo_bitfield_desc_s cpuinf_feat1 []
 
struct cpuinfo_bitfield_desc_s cpuinf_dbgfeat []
 
struct cpuinfo_bitfield_desc_s cpuinf_mmfr0 []
 
struct cpuinfo_bitfield_desc_s cpuinf_mmfr1 []
 
struct cpuinfo_bitfield_desc_s cpuinf_mmfr2 []
 
struct cpuinfo_bitfield_desc_s cpuinf_mmfr3 []
 
struct cpuinfo_bitfield_desc_s cpuinf_isar0 []
 
struct cpuinfo_bitfield_desc_s cpuinf_isar1 []
 
struct cpuinfo_bitfield_desc_s cpuinf_isar2 []
 
struct cpuinfo_bitfield_desc_s cpuinf_isar3 []
 
struct cpuinfo_bitfield_desc_s cpuinf_isar4 []
 
struct cpuinfo_bitfield_desc_s cpuinf_isar5 []
 
struct cpuinfo_bitfield_desc_s cpuinf_ctr []
 
struct cpuinfo_bitfield_desc_s cpuinf_clidr []
 
struct cpuinfo_bitfield_desc_s cpuinf_csselr []
 
struct cpuinfo_bitfield_desc_s cpuinf_ccsidr []
 
struct cpuinfo_bitfield_desc_s cpuinf_tcmreg []
 
struct cpuinfo_bitfield_desc_s cpuinf_mputype []
 
struct cpuinfo_bitfield_desc_s cpuinf_mpubase []
 
struct cpuinfo_bitfield_desc_s cpuinf_sctlr []
 
struct cpuinfo_bitfield_desc_s cpuinf_mpusizeen []
 
struct cpuinfo_bitfield_desc_s cpuinf_accesscontrol []
 
struct cpuinfo_bitfield_desc_s cpuinf_generic []
 
static struct
cpuinfo_bitfield_desc_s 
cpuinf_dbgdidr []
 
static struct
cpuinfo_bitfield_desc_s 
cpuinf_dbgd_address []
 
static struct
cpuinfo_bitfield_desc_s 
cpuinf_dbgdscr []
 
struct cpuinfo_word_desc_s cpuinfo_desc_pmsa []
 
struct cpuinfo_bitfield_desc_s cpuinf_tlbtype []
 
struct cpuinfo_bitfield_desc_s cpuinf_sctlr_vmsa []
 
struct cpuinfo_bitfield_desc_s cpuinf_clidr_vmsa []
 
struct cpuinfo_bitfield_desc_s cpuinf_ttbcr []
 
struct cpuinfo_bitfield_desc_s cpuinf_ttbr0 []
 
struct cpuinfo_bitfield_desc_s cpuinf_ttbr1 []
 
struct cpuinfo_bitfield_desc_s cpuinf_actlr_vmsa []
 
struct cpuinfo_bitfield_desc_s cpuinf_cpacr_vmsa []
 
struct cpuinfo_word_desc_s cpuinfo_desc_vmsa []
 
char * cpolicies []
 
const char * csvhead = "Virt.addr,Table,Type,P bit,NG bit,Domain,Phys.addr,L2 ref,S bit,Privileged/Nonpriv.,Caching,Memtype,XN bit\n"
 

Dokumentation der Funktionen

void __attribute__ ( (naked, noinline)  )

Definiert in Zeile 539 der Datei cpuinfo_v7.c.

539  {
540  asm (
541  ".syntax unified\n"
542  ".code 16\n"
543  ".align 2\n"
544  "BX PC\n" // switch to ARM mode
545  ".code 32\n"
546 
547  "MRC p15, 0, R1,c0,c0\n" // ident
548  "STR R1, [R0]\n"
549 
550  "MRC p15, 0, R1,c0,c0,1\n" // cache
551  "ADD R0, R0, #4\n"
552  "STR R1, [R0]\n"
553 
554  "MRC p15, 0, R1,c0,c0,2\n" // TCM
555  "ADD R0, R0, #4\n"
556  "STR R1, [R0]\n"
557 
558  "MRC p15, 0, R1,c0,c0,4\n" // MPU
559  "ADD R0, R0, #4\n"
560  "STR R1, [R0]\n"
561 
562  "MRC p15, 0, R1,c0,c0,5\n" // MPIDR
563  "ADD R0, R0, #4\n"
564  "STR R1, [R0]\n"
565 
566  "MRC p15, 0, R1,c0,c1,0\n" // ID_PFR0
567  "ADD R0, R0, #4\n"
568  "STR R1, [R0]\n"
569 
570  "MRC p15, 0, R1,c0,c1,1\n" // ID_PFR1
571  "ADD R0, R0, #4\n"
572  "STR R1, [R0]\n"
573 
574  "MRC p15, 0, R1,c0,c1,2\n" // ID_DFR0
575  "ADD R0, R0, #4\n"
576  "STR R1, [R0]\n"
577 
578  "MRC p15, 0, R1,c0,c1,3\n" // ID_AFR0
579  "ADD R0, R0, #4\n"
580  "STR R1, [R0]\n"
581 
582  "MRC p15, 0, R1,c0,c1,4\n" // ID_MMFR0
583  "ADD R0, R0, #4\n"
584  "STR R1, [R0]\n"
585 
586  "MRC p15, 0, R1,c0,c1,5\n" // ID_MMFR1
587  "ADD R0, R0, #4\n"
588  "STR R1, [R0]\n"
589 
590  "MRC p15, 0, R1,c0,c1,6\n" // ID_MMFR2
591  "ADD R0, R0, #4\n"
592  "STR R1, [R0]\n"
593 
594  "MRC p15, 0, R1,c0,c1,7\n" // ID_MMFR3
595  "ADD R0, R0, #4\n"
596  "STR R1, [R0]\n"
597 
598  "MRC p15, 0, R1,c0,c2,0\n" // ID_ISAR0
599  "ADD R0, R0, #4\n"
600  "STR R1, [R0]\n"
601 
602  "MRC p15, 0, R1,c0,c2,1\n" // ID_ISAR1
603  "ADD R0, R0, #4\n"
604  "STR R1, [R0]\n"
605 
606  "MRC p15, 0, R1,c0,c2,2\n" // ID_ISAR2
607  "ADD R0, R0, #4\n"
608  "STR R1, [R0]\n"
609 
610  "MRC p15, 0, R1,c0,c2,3\n" // ID_ISAR3
611  "ADD R0, R0, #4\n"
612  "STR R1, [R0]\n"
613 
614  "MRC p15, 0, R1,c0,c2,4\n" // ID_ISAR4
615  "ADD R0, R0, #4\n"
616  "STR R1, [R0]\n"
617 
618  "MRC p15, 0, R1,c0,c2,5\n" // ID_ISAR5
619  "ADD R0, R0, #4\n"
620  "STR R1, [R0]\n"
621 
622  "MRC p15, 1, R1,c0,c0,1\n" // CLIDR
623  "ADD R0, R0, #4\n"
624  "STR R1, [R0]\n"
625 
626  "MOV R1, #0\n"
627  "MCR p15, 2, R1,c0,c0,0\n" // CSSELR (data cache, level0)
628 
629  "MRC p15, 1, R1,c0,c0,0\n" // CCSIDR (the currently selected one)
630  "ADD R0, R0, #4\n"
631  "STR R1, [R0]\n"
632 
633  "MOV R1, #1\n"
634  "MCR p15, 2, R1,c0,c0,0\n" // CSSELR (inst cache, level0)
635 
636  "MRC p15, 1, R1,c0,c0,0\n" // CCSIDR (the currently selected one)
637  "ADD R0, R0, #4\n"
638  "STR R1, [R0]\n"
639 
640  "MRC p15, 0, R1,c1,c0,0\n" // SCTLR
641  "ADD R0, R0, #4\n"
642  "STR R1, [R0]\n"
643 
644  "MRC p15, 0, R1,c1,c0,1\n" // ACTLR
645  "ADD R0, R0, #4\n"
646  "STR R1, [R0]\n"
647 
648 //#ifndef CONFIG_QEMU
649  "MRC p15, 0, R1,c15,c0,0\n" // ACTLR2
650  "ADD R0, R0, #4\n"
651  "STR R1, [R0]\n"
652 //#endif
653 
654  "MRC p15, 0, R1,c1,c0,2\n" // CPACR
655  "ADD R0, R0, #4\n"
656  "STR R1, [R0]\n"
657 
658  "MRC p15, 0, R1,c15,c2,0\n" // Build options 1 reg (from Cortex R4 TRM)
659  "ADD R0, R0, #4\n"
660  "STR R1, [R0]\n"
661 
662  "MRC p15, 0, R1,c15,c2,1\n" // Build options 2 reg (from Cortex R4 TRM)
663  "ADD R0, R0, #4\n"
664  "STR R1, [R0]\n"
665 
666  "MRC p15, 0, R1,c9,c1,1\n" // ATCM region reg
667  "ADD R0, R0, #4\n"
668  "STR R1, [R0]\n"
669 
670  "MRC p15, 0, R1,c9,c1,0\n" // BTCM region reg
671  "ADD R0, R0, #4\n"
672  "STR R1, [R0]\n"
673 
674  "MOV R1, #0\n"
675  "MCR p15, 0, R1,c6,c2,0\n" // MPU Memory Region Number Register, region 0
676 
677  "MRC p15, 0, R1,c6,c1,0\n" // MPU region base register
678  "ADD R0, R0, #4\n"
679  "STR R1, [R0]\n"
680  "MRC p15, 0, R1,c6,c1,2\n" // MPU Region Size and Enable Register
681  "ADD R0, R0, #4\n"
682  "STR R1, [R0]\n"
683  "MRC p15, 0, R1,c6,c1,4\n" // MPU Region Access Control Register
684  "ADD R0, R0, #4\n"
685  "STR R1, [R0]\n"
686 
687  "MOV R1, #1\n"
688  "MCR p15, 0, R1,c6,c2,0\n" // region 1
689 
690  "MRC p15, 0, R1,c6,c1,0\n" // MPU region base register
691  "ADD R0, R0, #4\n"
692  "STR R1, [R0]\n"
693  "MRC p15, 0, R1,c6,c1,2\n" // MPU Region Size and Enable Register
694  "ADD R0, R0, #4\n"
695  "STR R1, [R0]\n"
696  "MRC p15, 0, R1,c6,c1,4\n" // MPU Region Access Control Register
697  "ADD R0, R0, #4\n"
698  "STR R1, [R0]\n"
699 
700  "MOV R1, #2\n"
701  "MCR p15, 0, R1,c6,c2,0\n" // region 2
702 
703  "MRC p15, 0, R1,c6,c1,0\n" // MPU region base register
704  "ADD R0, R0, #4\n"
705  "STR R1, [R0]\n"
706  "MRC p15, 0, R1,c6,c1,2\n" // MPU Region Size and Enable Register
707  "ADD R0, R0, #4\n"
708  "STR R1, [R0]\n"
709  "MRC p15, 0, R1,c6,c1,4\n" // MPU Region Access Control Register
710  "ADD R0, R0, #4\n"
711  "STR R1, [R0]\n"
712 
713  "MOV R1, #3\n"
714  "MCR p15, 0, R1,c6,c2,0\n" // region 3
715 
716  "MRC p15, 0, R1,c6,c1,0\n" // MPU region base register
717  "ADD R0, R0, #4\n"
718  "STR R1, [R0]\n"
719  "MRC p15, 0, R1,c6,c1,2\n" // MPU Region Size and Enable Register
720  "ADD R0, R0, #4\n"
721  "STR R1, [R0]\n"
722  "MRC p15, 0, R1,c6,c1,4\n" // MPU Region Access Control Register
723  "ADD R0, R0, #4\n"
724  "STR R1, [R0]\n"
725 
726  "MOV R1, #4\n"
727  "MCR p15, 0, R1,c6,c2,0\n" // region 4
728 
729  "MRC p15, 0, R1,c6,c1,0\n" // MPU region base register
730  "ADD R0, R0, #4\n"
731  "STR R1, [R0]\n"
732  "MRC p15, 0, R1,c6,c1,2\n" // MPU Region Size and Enable Register
733  "ADD R0, R0, #4\n"
734  "STR R1, [R0]\n"
735  "MRC p15, 0, R1,c6,c1,4\n" // MPU Region Access Control Register
736  "ADD R0, R0, #4\n"
737  "STR R1, [R0]\n"
738 
739  "MOV R1, #5\n"
740  "MCR p15, 0, R1,c6,c2,0\n" // region 5
741 
742  "MRC p15, 0, R1,c6,c1,0\n" // MPU region base register
743  "ADD R0, R0, #4\n"
744  "STR R1, [R0]\n"
745  "MRC p15, 0, R1,c6,c1,2\n" // MPU Region Size and Enable Register
746  "ADD R0, R0, #4\n"
747  "STR R1, [R0]\n"
748  "MRC p15, 0, R1,c6,c1,4\n" // MPU Region Access Control Register
749  "ADD R0, R0, #4\n"
750  "STR R1, [R0]\n"
751 
752  "MOV R1, #6\n"
753  "MCR p15, 0, R1,c6,c2,0\n" // region 6
754 
755  "MRC p15, 0, R1,c6,c1,0\n" // MPU region base register
756  "ADD R0, R0, #4\n"
757  "STR R1, [R0]\n"
758  "MRC p15, 0, R1,c6,c1,2\n" // MPU Region Size and Enable Register
759  "ADD R0, R0, #4\n"
760  "STR R1, [R0]\n"
761  "MRC p15, 0, R1,c6,c1,4\n" // MPU Region Access Control Register
762  "ADD R0, R0, #4\n"
763  "STR R1, [R0]\n"
764 
765  "MOV R1, #7\n"
766  "MCR p15, 0, R1,c6,c2,0\n" // region 7
767 
768  "MRC p15, 0, R1,c6,c1,0\n" // MPU region base register
769  "ADD R0, R0, #4\n"
770  "STR R1, [R0]\n"
771  "MRC p15, 0, R1,c6,c1,2\n" // MPU Region Size and Enable Register
772  "ADD R0, R0, #4\n"
773  "STR R1, [R0]\n"
774  "MRC p15, 0, R1,c6,c1,4\n" // MPU Region Access Control Register
775  "ADD R0, R0, #4\n"
776  "STR R1, [R0]\n"
777 
778  "MRC p14, 0, R1,c0,c0,0\n" // DBGDIDR
779  "ADD R0, R0, #4\n"
780  "STR R1, [R0]\n"
781 
782  "MRC p14, 0, R1,c1,c0,0\n" // DBGDRAR
783  "ADD R0, R0, #4\n"
784  "STR R1, [R0]\n"
785 
786  "MRC p14, 0, R1,c2,c0,0\n" // DBGDSAR
787  "ADD R0, R0, #4\n"
788  "STR R1, [R0]\n"
789 
790  "MRC p14, 0, R1,c0,c1,0\n" // DBGDSCR
791  "ADD R0, R0, #4\n"
792  "STR R1, [R0]\n"
793 
794  //".word 0xEEF01A10\n" //"VMRS R1, FPSID\n" // Floating Point System ID register
795  //"ADD R0, R0, #4\n"
796  //"STR R1, [R0]\n"
797 
798  //".word 0xEEF71A10\n" //"VMRS R1, MVFR0\n" // Media and VFP Feature Register 0
799  //"ADD R0, R0, #4\n"
800  //"STR R1, [R0]\n"
801 
802  //".word 0xEEF61A10\n" //"VMRS R1, MVFR1\n" // Media and VFP Feature Register 1
803  //"ADD R0, R0, #4\n"
804  //"STR R1, [R0]\n"
805 
806  "BX LR\n"
807 
808  :::"r0","r1"
809  );
810 }
static const char* bitfield8 ( unsigned  val)
static

Definiert in Zeile 343 der Datei cpuinfo_v7.c.

343  {
344  linebuf[8] = 0;
345  int n;
346  for (n=0; n<8; n++) {
347  linebuf[7-n] = (val & (1<<n))?'1':'0';
348  }
349  return linebuf;
350 }
static const char* cache_tcm_addr_str ( unsigned  val)
static

Definiert in Zeile 280 der Datei cpuinfo_v7.c.

280  {
281  sprintf(linebuf,"0x%08x",val<<12);
282  return linebuf;
283 }
static const char* cache_tcm_size_str ( unsigned  val)
static

Definiert in Zeile 272 der Datei cpuinfo_v7.c.

272  {
273  if (val == 0)
274  return "0";
275  if (val < 3 || val > 14)
276  return "invalid";
277  return reg_sizes[val-3];
278 }
static const char* ccsidr_linesize ( unsigned  val)
static

Definiert in Zeile 252 der Datei cpuinfo_v7.c.

252  {
253  return two_nth_str[val+2];
254 }
static const char* ccsidr_plusone ( unsigned  val)
static

Definiert in Zeile 256 der Datei cpuinfo_v7.c.

256  {
257  sprintf(linebuf,"%i",val+1);
258  return linebuf;
259 }
static const char* ctype_str ( unsigned  val)
static

Definiert in Zeile 219 der Datei cpuinfo_v7.c.

219  {
220  switch (val) {
221  case 0: return "no cache";
222  case 1: return "Icache only";
223  case 2: return "Dcache only";
224  case 3: return "Separate Icache, Dcache";
225  case 4: return "Unified cache";
226  }
227  return "-";
228 }
static const char* dbg_version ( unsigned  val)
static

Definiert in Zeile 410 der Datei cpuinfo_v7.c.

410  {
411  switch(val) {
412  case 0b0001: return "v6";
413  case 0b0010: return "v6.1";
414  case 0b0011: return "v7 full";
415  case 0b0100: return "v7 basic";
416  case 0b0101: return "v7.1";
417  case 0b0110: return "v8";
418  case 0b0111: return "v8.1";
419  case 0b1000: return "v8.2";
420  }
421  return "???";
422 }
unsigned interpret_l1_table_entry ( unsigned  e,
char *  buf 
)

Definiert in Zeile 1281 der Datei cpuinfo_v7.c.

1281  {
1282  unsigned ret = 0, l2a = 0;
1283  struct l1tblentry_s col;
1284  col.typ = "";
1285  col.pbit = "";
1286  col.ngbit = "";
1287  col.domain = 0;
1288  col.physaddr[0] = 0;
1289  col.l2addr[0] = 0;
1290  col.sbit = "";
1291  col.accperm = "";
1292  col.caching = "";
1293  col.memtype = "";
1294  col.xnbit = "";
1295  int typ = -1;
1296  switch (e & 3) {
1297  case 1: typ = 2;
1298  break;
1299  case 2: typ = (e & 0x40000)?1:0;
1300  break;
1301  }
1302  if (typ < 0) {
1303  sprintf(buf,"Fault,");
1304  return 2;
1305  }
1306  if (e & 0x200) {
1307  col.pbit = "P";
1308  }
1309  col.domain = (e >> 5) & 15;
1310  if (typ == 2) {
1311  col.typ = "L2 ref";
1312  l2a = e & 0xfffffc00;
1313  sprintf(col.l2addr,"0x%08x",l2a);
1314  }
1315  else {
1316  col.typ = typ==1?"Supersection":"Section";
1317  sprintf(col.physaddr,"0x%08x",e & 0xfff00000);
1318  col.ngbit = e&0x20000?"Nonglobal":"Global";
1319  col.sbit = e&0x10000?"Shareable":"";
1320  col.xnbit = e&0x10?"No exec":"";
1321  switch (e & 0x8C00) {
1322  case 0: col.accperm = "--/--"; break;
1323  case 0x400: col.accperm = "RW/--"; break;
1324  case 0x800: col.accperm = "RW/R-"; break;
1325  case 0xC00: col.accperm = "RW/RW"; break;
1326  case 0x8000: col.accperm = "rsrvd"; break;
1327  case 0x8400: col.accperm = "R-/--"; break;
1328  case 0x8800: col.accperm = "R-/R-"; break;
1329  case 0x8C00: col.accperm = "rsrvd"; break;
1330  }
1331  switch (e & 0x700c) {
1332  case 0: col.caching = "STR ORD"; col.memtype = "Strongly-ordered"; break;
1333  case 4: col.caching = "SHR DEV"; col.memtype = "Device"; break;
1334  case 8: col.caching = "WRTHR, NAW"; col.memtype = "Normal"; break;
1335  case 0xc: col.caching = "WRBCK, NAW"; col.memtype = "Normal"; break;
1336  case 0x1000: col.caching = "NON CACH"; col.memtype = "Normal"; break;
1337  case 0x2000: col.caching = "NONSHR DEV"; col.memtype = "Device"; break;
1338  default:
1339  if (e & 0x4000) {
1340  unsigned i = ((e&0x3000)>>10)|((e&0xc)>>2);
1341  col.caching = cpolicies[i];
1342  col.memtype = "Normal";
1343  }
1344  }
1345  }
1346  sprintf(buf,"%s,%s,%s,%u,%s,%s,%s,%s,%s,%s,%s,",col.typ,col.pbit,
1347  col.ngbit,col.domain,col.physaddr,col.l2addr,col.sbit,col.accperm,
1348  col.caching,col.memtype,col.xnbit);
1349  if (typ==1) {
1350  ret = 1;
1351  }
1352  if (l2a!=0) {
1353  ret = l2a;
1354  }
1355  return ret;
1356 }
unsigned interpret_l2_table_entry ( unsigned  e,
char *  buf 
)

Definiert in Zeile 1358 der Datei cpuinfo_v7.c.

1358  {
1359  unsigned ret = 0, f;
1360  struct l1tblentry_s col;
1361  col.typ = "";
1362  col.pbit = "";
1363  col.ngbit = "";
1364  col.domain = 0;
1365  col.physaddr[0] = 0;
1366  col.l2addr[0] = 0;
1367  col.sbit = "";
1368  col.accperm = "";
1369  col.caching = "";
1370  col.memtype = "";
1371  col.xnbit = "";
1372  int typ = -1;
1373  switch (e & 3) {
1374  case 1: typ = 1;
1375  col.typ = "Large page";
1376  sprintf(col.physaddr,"0x%08x",e & 0xffff0000);
1377  col.xnbit = e&0x8000?"No exec":"";
1378  f = e;
1379  break;
1380  case 2:
1381  case 3: typ = 0;
1382  col.typ = "Small page";
1383  sprintf(col.physaddr,"0x%08x",e & 0xfffff000);
1384  col.xnbit = e&1?"No exec":"";
1385  f = ((e<<6) & 0x7000) | (e & 0xc); // rearrange bits for evaluation below
1386  break;
1387  }
1388  if (typ < 0) {
1389  sprintf(buf,"Fault,");
1390  return 2;
1391  }
1392  col.ngbit = e&0x800?"Nonglobal":"Global";
1393  col.sbit = e&0x400?"Shareable":"";
1394  switch ((e<<6) & 0x8C00) {
1395  case 0: col.accperm = "--/--"; break;
1396  case 0x400: col.accperm = "RW/--"; break;
1397  case 0x800: col.accperm = "RW/R-"; break;
1398  case 0xC00: col.accperm = "RW/RW"; break;
1399  case 0x8000: col.accperm = "rsrvd"; break;
1400  case 0x8400: col.accperm = "R-/--"; break;
1401  case 0x8800: col.accperm = "R-/R-"; break;
1402  case 0x8C00: col.accperm = "rsrvd"; break;
1403  }
1404  switch (f & 0x700c) {
1405  case 0: col.caching = "STR ORD"; col.memtype = "Strongly-ordered"; break;
1406  case 4: col.caching = "SHR DEV"; col.memtype = "Device"; break;
1407  case 8: col.caching = "WRTHR, NAW"; col.memtype = "Normal"; break;
1408  case 0xc: col.caching = "WRBCK, NAW"; col.memtype = "Normal"; break;
1409  case 0x1000: col.caching = "NON CACH"; col.memtype = "Normal"; break;
1410  case 0x2000: col.caching = "NONSHR DEV"; col.memtype = "Device"; break;
1411  default:
1412  if (f & 0x4000) {
1413  unsigned i = ((f&0x3000)>>10)|((f&0xc)>>2);
1414  col.caching = cpolicies[i];
1415  col.memtype = "Normal";
1416  }
1417  }
1418  sprintf(buf,"%s,%s,%s,,%s,%s,%s,%s,%s,%s,%s,",col.typ,col.pbit,
1419  col.ngbit,col.physaddr,col.l2addr,col.sbit,col.accperm,
1420  col.caching,col.memtype,col.xnbit);
1421  if (typ==1) {
1422  ret = 1;
1423  }
1424  return ret;
1425 }
void memmapping_vmsa ( FILE f)

Definiert in Zeile 1429 der Datei cpuinfo_v7.c.

1429  {
1430  struct mmuregs_s mmuregs;
1431  get_mmuregs_vmsa(&mmuregs);
1432  unsigned tt0len = 128 << (7 - (mmuregs.ttbcr & 7));
1433  unsigned tt0adr = mmuregs.ttbr0 & 0xffffff80;
1434  unsigned tt1adr = mmuregs.ttbr1 & 0xffffff80;
1435  unsigned n, *e, r, pr=42, cycl, l1a;
1436  char *conclude;
1437  e = (unsigned*)tt0adr;
1438  cycl = tt0len/4;
1439  l1a = 0;
1440  unsigned remain = 2;
1441  fwrite(csvhead,1,strlen(csvhead),f);
1442  while (remain) {
1443  for (n=0; n<cycl; n++) {
1444  sprintf(linebuf,"0x%08X,L1,",l1a); // virtual address to be described by L1 entry
1445  fwrite(linebuf,1,strlen(linebuf),f);
1446  conclude = "\n";
1448  fwrite(linebuf,1,strlen(linebuf),f);
1449  if (r==1 && pr!=1) { // supersection begins
1450  if ((unsigned)e & 0x3f) {
1451  conclude = "ERR: Unaligned supersection\n";
1452  }
1453  else {
1454  unsigned m, v;
1455  v = *e;
1456  for (m=1; m<16; m++) {
1457  if (v != *(e+m)) {
1458  conclude = "ERR: Inconsistent supersection\n";
1459  break;
1460  }
1461  }
1462  }
1463  }
1464  else if (r==2) {
1465  conclude = "\n";
1466  }
1467  fwrite(conclude,1,strlen(conclude),f);
1468  if (r>42) { // interpret L2 table
1469  unsigned nn, l2a, *ee, rr, prr=42;
1470  l2a = l1a;
1471  ee = (unsigned*) r;
1472  for (nn=0; nn<256; nn++) {
1473  sprintf(linebuf,"0x%08X,L2,",l2a); // virtual address to be described by L2 entry
1474  fwrite(linebuf,1,strlen(linebuf),f);
1475  conclude = "\n";
1476  rr = interpret_l2_table_entry(*ee, linebuf);
1477  fwrite(linebuf,1,strlen(linebuf),f);
1478 
1479  if (rr==1 && prr!=1) { // large page begins
1480  if ((unsigned)ee & 0x3f) {
1481  conclude = "ERR: Unaligned large page\n";
1482  }
1483  else {
1484  unsigned mm, vv;
1485  vv = *ee;
1486  for (mm=1; mm<16; mm++) {
1487  if (vv != *(ee+mm)) {
1488  conclude = "ERR: Inconsistent large page\n";
1489  break;
1490  }
1491  }
1492  }
1493  }
1494  else if (rr==2) {
1495  conclude = "\n";
1496  }
1497  fwrite(conclude,1,strlen(conclude),f);
1498 
1499  ee++;
1500  prr = rr;
1501  l2a += 0x1000;
1502  }
1503  }
1504  e++;
1505  pr = r;
1506  l1a += 0x100000;
1507  }
1508  e = (unsigned*)(tt1adr+tt0len);
1509  cycl = (0x4000 - tt0len) / 4;
1510  remain--;
1511  }
1512  fclose(f);
1513 }
static const char* mmfr3_bp ( unsigned  val)
static

Definiert in Zeile 104 der Datei cpuinfo_v7.c.

104  {
105  switch (val) {
106  case 0: return "Not supported";
107  case 1: return "Invalidate all";
108  case 2: return "Invalidate all, invalidate by MVA";
109  }
110  return "(invalid)";
111 }
static const char* mmfr3_cache ( unsigned  val)
static

Definiert in Zeile 96 der Datei cpuinfo_v7.c.

96  {
97  switch (val) {
98  case 0: return "Not supported";
99  case 1: return "Supported";
100  }
101  return "(invalid)";
102 }
static const char* mmfr3_cms ( unsigned  val)
static

Definiert in Zeile 113 der Datei cpuinfo_v7.c.

113  {
114  switch (val) {
115  case 0: return "4 GByte";
116  case 1: return "64 GByte";
117  case 2: return "1 TByte";
118  }
119  return "(invalid)";
120 }
static const char* mmfr3_ss ( unsigned  val)
static

Definiert in Zeile 122 der Datei cpuinfo_v7.c.

122  {
123  switch (val) {
124  case 0: return "Supported";
125  case 15: return "Not supported";
126  }
127  return "(invalid)";
128 }
static const char* mpu_rattr ( unsigned  val)
static

Definiert in Zeile 360 der Datei cpuinfo_v7.c.

360  {
361  char *s="";
362  char *s2="";
363  char *t;
364  t = (val&4)?"Shared":"Non-shared";
365  if (val&0x20) {
366  switch (val&3) {
367  case 0: s = "Inner Non-cacheable"; break;
368  case 1: s = "Inner Write-back, write-allocate"; break;
369  case 2: s = "Inner Write-through, no write-allocate"; break;
370  case 3: s = "Inner Write-back, no write-allocate"; break;
371  }
372  switch ((val&0x18)>>3) {
373  case 0: s2 = "Outer Non-cacheable"; break;
374  case 1: s2 = "Outer Write-back, write-allocate"; break;
375  case 2: s2 = "Outer Write-through, no write-allocate"; break;
376  case 3: s2 = "Outer Write-back, no write-allocate"; break;
377  }
378  sprintf(linebuf,"%s; %s; %s",s, s2, t);
379  }
380  else {
381  switch (val&0x1B) {
382  case 0: s = "Strongly ordered, shareable"; t=""; break;
383  case 1: s = "Shareable device"; t="Shareable"; break;
384  case 2: s = "Outer and Inner write-through, no write-allocate"; break;
385  case 3: s = "Outer and Inner write-back, no write-allocate"; break;
386  case 8: s = "Outer and Inner Non-cacheable"; break;
387  case 11: s = "Outer and Inner write-back, write-allocate"; break;
388  case 16: s = "Non-shareable Device"; t=""; break;
389  default: s = "(reserved)"; t="";
390  }
391  sprintf(linebuf,"%s; %s",s, t);
392  }
393  return linebuf;
394 }
static const char* mpu_region_size_str ( unsigned  val)
static

Definiert in Zeile 335 der Datei cpuinfo_v7.c.

335  {
336  if (val < 4 || val > 31)
337  return "invalid";
338  if (val < 11)
339  return two_nth_str[val+1];
340  return reg_sizes[val-11];
341 }
static const char* tlb_entries ( unsigned  val)
static

Definiert in Zeile 820 der Datei cpuinfo_v7.c.

820  {
821  switch(val) {
822  case 0: return "64";
823  case 1: return "128";
824  case 2: return "256";
825  case 3: return "512";
826  }
827  return "???";
828 }
static const char* tlb_unified ( unsigned  val)
static

Definiert in Zeile 812 der Datei cpuinfo_v7.c.

812  {
813  switch(val) {
814  case 0: return "Unified TLB";
815  case 1: return "Separate data and instruction TLB";
816  }
817  return "???";
818 }
static const char* ttbcr_n ( unsigned  val)
static

Definiert in Zeile 898 der Datei cpuinfo_v7.c.

898  {
899  val = 128 << (7-val);
900  sprintf(linebuf,"TTBR0 table size %u bytes",val);
901  return linebuf;
902 }
static const char* ttbraddr0 ( unsigned  val)
static

Definiert in Zeile 886 der Datei cpuinfo_v7.c.

886  {
887  val <<= 7;
888  sprintf(linebuf,"0x%08x",val);
889  return linebuf;
890 }
static const char* ttbraddr1 ( unsigned  val)
static

Definiert in Zeile 892 der Datei cpuinfo_v7.c.

892  {
893  val <<= 7;
894  sprintf(linebuf,"0x%08x",val);
895  return linebuf;
896 }
static const char* two_on_nth ( unsigned  val)
static

Definiert in Zeile 9 der Datei cpuinfo_v7.c.

9  {
10  if (val < 16) {
11  return two_nth_str[val];
12  }
13  return "invalid";
14 }
static const char* two_on_nth_granule ( unsigned  val)
static

Definiert in Zeile 16 der Datei cpuinfo_v7.c.

16  {
17  if (val == 0) {
18  return "no info";
19  }
20  else if (val > 9) {
21  return "reserved";
22  }
23  else {
24  return two_nth_str[val];
25  }
26  return "invalid";
27 }

Variablen-Dokumentation

char* cpolicies[]
Initialisierung:
= {
"Cached OUTER 0 INNER 0",
"Cached OUTER 0 INNER 1",
"Cached OUTER 0 INNER 2",
"Cached OUTER 0 INNER 3",
"Cached OUTER 1 INNER 0",
"Cached OUTER 1 INNER 1",
"Cached OUTER 1 INNER 2",
"Cached OUTER 1 INNER 3",
"Cached OUTER 2 INNER 0",
"Cached OUTER 2 INNER 1",
"Cached OUTER 2 INNER 2",
"Cached OUTER 2 INNER 3",
"Cached OUTER 3 INNER 0",
"Cached OUTER 3 INNER 1",
"Cached OUTER 3 INNER 2",
"Cached OUTER 3 INNER 3",
}

Definiert in Zeile 1262 der Datei cpuinfo_v7.c.

struct cpuinfo_bitfield_desc_s cpuinf_accesscontrol[]
Initialisierung:
= {
{6,"Region attributes", mpu_rattr},
{2,"-"},
{3,"Access permission", regperm_str},
{1,"-"},
{1,"Execute never"},
{}
}

Definiert in Zeile 396 der Datei cpuinfo_v7.c.

struct cpuinfo_bitfield_desc_s cpuinf_actlr_vmsa[]
Initialisierung:
= {
{1,"Cache & TLB maint. broadcast" },
{1,"L2 prefetch enable" },
{1,"L1 prefetch enable" },
{1,"Write full line of zeroes" },
{2,"(zero)"},
{1,"SMP" },
{1,"Exclusive cache" },
{1,"Alloc in one way" },
{1,"Parity on" },
{22,"-"},
{}
}

Definiert in Zeile 936 der Datei cpuinfo_v7.c.

struct cpuinfo_bitfield_desc_s cpuinf_ccsidr[]
Initialisierung:
= {
{3,"Line size in words", ccsidr_linesize},
{10,"Associativity", ccsidr_plusone},
{15,"Number of sets", ccsidr_plusone},
{1,"Write allocation"},
{1,"Read allocation"},
{1,"Write back"},
{1,"Write through"},
{}
}

Definiert in Zeile 261 der Datei cpuinfo_v7.c.

struct cpuinfo_bitfield_desc_s cpuinf_clidr[]
Initialisierung:
= {
{3,"Cache type, level1", ctype_str},
{3,"Cache type, level2", ctype_str},
{3,"Cache type, level3", ctype_str},
{3,"Cache type, level4", ctype_str},
{3,"Cache type, level5", ctype_str},
{3,"Cache type, level6", ctype_str},
{3,"Cache type, level7", ctype_str},
{3,"Cache type, level8", ctype_str},
{3,"Level of coherency"},
{3,"Level of unification"},
{2,"(zero)"},
{}
}

Definiert in Zeile 230 der Datei cpuinfo_v7.c.

struct cpuinfo_bitfield_desc_s cpuinf_clidr_vmsa[]
Initialisierung:
= {
{3,"Cache type, level1", ctype_str},
{3,"Cache type, level2", ctype_str},
{3,"Cache type, level3", ctype_str},
{3,"Cache type, level4", ctype_str},
{3,"Cache type, level5", ctype_str},
{3,"Cache type, level6", ctype_str},
{3,"Cache type, level7", ctype_str},
{3,"Level of unification Inner Shareable"},
{3,"Level of coherency"},
{3,"Level of unification"},
{2,"(zero)"},
{}
}

Definiert in Zeile 871 der Datei cpuinfo_v7.c.

struct cpuinfo_bitfield_desc_s cpuinf_cpacr_vmsa[]
Initialisierung:
= {
{20,"(zero)"},
{2,"CP10 access permission" },
{2,"CP11 access permission" },
{6,"(zero)"},
{1,"D32DIS" },
{1,"ASEDIS" },
{}
}

Definiert in Zeile 950 der Datei cpuinfo_v7.c.

struct cpuinfo_bitfield_desc_s cpuinf_csselr[]
Initialisierung:
= {
{1,"Instruction, not data"},
{3,"Level"},
{28,"(unknown)"},
{}
}

Definiert in Zeile 245 der Datei cpuinfo_v7.c.

struct cpuinfo_bitfield_desc_s cpuinf_ctr[]
Initialisierung:
= {
{4,"Icache min words/line", two_on_nth},
{10,"(zero)"},
{2,"L1 Icache policy"},
{4,"Dcache min words/line", two_on_nth},
{4,"Exclusives Reservation Granule", two_on_nth_granule},
{4,"Cache Writeback Granule", two_on_nth_granule},
{1,"(zero)"},
{3,"(register format)"},
{}
}

Definiert in Zeile 207 der Datei cpuinfo_v7.c.

struct cpuinfo_bitfield_desc_s cpuinf_dbgd_address[]
static
Initialisierung:
= {
{2,"Valid"},
{10,"- (UNK)"},
{20,"Address",cache_tcm_addr_str},
{}
}

Definiert in Zeile 435 der Datei cpuinfo_v7.c.

struct cpuinfo_bitfield_desc_s cpuinf_dbgdidr[]
static
Initialisierung:
= {
{4,"Revision"},
{4,"Variant"},
{8,"- (RAZ)"},
{4,"Version",dbg_version},
{4,"Context",ccsidr_plusone},
{4,"BRP",ccsidr_plusone},
{4,"WRP",ccsidr_plusone},
{}
}

Definiert in Zeile 424 der Datei cpuinfo_v7.c.

struct cpuinfo_bitfield_desc_s cpuinf_dbgdscr[]
static
Initialisierung:
= {
{1,"HALTED"},
{1,"RESTARTED"},
{4,"MOE"},
{1,"SDABORT_l"},
{1,"ADABORT_l"},
{1,"UND_l"},
{1,"FS"},
{1,"DBGack"},
{1,"INTdis"},
{1,"UDCCdis"},
{1,"ITRen"},
{1,"HDBGen"},
{1,"MDBGen"},
{1,"SPIDdis"},
{1,"SPNIDdis"},
{1,"NS"},
{1,"ADAdiscard"},
{2,"ExtDCCmode"},
{2,"- (SBZ)"},
{1,"InstrCompl_l"},
{1,"PipeAdv"},
{1,"TXfull_l"},
{1,"RXfull_l"},
{1,"- (SBZ)"},
{1,"TXfull"},
{1,"RXfull"},
{1,"- (SBZ)"},
{}
}

Definiert in Zeile 442 der Datei cpuinfo_v7.c.

struct cpuinfo_bitfield_desc_s cpuinf_dbgfeat[]
Initialisierung:
= {
{4,"Coproc. dbg model"},
{4,"Coproc. secure dbg model"},
{4,"Memory-mapped dbg model"},
{4,"Coproc. trace model"},
{4,"Memory-mapped trace model"},
{4,"Debug model M"},
{4,"Perf. monitors"},
{4,"-"},
{}
}

Definiert in Zeile 48 der Datei cpuinfo_v7.c.

struct cpuinfo_bitfield_desc_s cpuinf_feat0[]
Initialisierung:
= {
{4,"ARM inst set"},
{4,"Thumb inst set"},
{4,"Jazelle inst set"},
{4,"ThumbEE inst set"},
{16,"-"},
{}
}

Definiert in Zeile 29 der Datei cpuinfo_v7.c.

struct cpuinfo_bitfield_desc_s cpuinf_feat1[]
Initialisierung:
= {
{4,"Programmers' model"},
{4,"Security extensions"},
{4,"Microcontr. prog model"},
{4,"Virt. extensions"},
{4,"Generic timer ext."},
{12,"-"},
{}
}

Definiert in Zeile 38 der Datei cpuinfo_v7.c.

struct cpuinfo_bitfield_desc_s cpuinf_generic[]
Initialisierung:
= {
{32,"(raw value)"},
{}
}

Definiert in Zeile 405 der Datei cpuinfo_v7.c.

struct cpuinfo_bitfield_desc_s cpuinf_isar0[]
Initialisierung:
= {
{4,"Swap instrs"},
{4,"Bitcount instrs"},
{4,"Bitfield instrs"},
{4,"CmpBranch instrs"},
{4,"Coproc instrs"},
{4,"Debug instrs"},
{4,"Divide instrs"},
{4,"-"},
{}
}

Definiert in Zeile 142 der Datei cpuinfo_v7.c.

struct cpuinfo_bitfield_desc_s cpuinf_isar1[]
Initialisierung:
= {
{4,"Endian instrs"},
{4,"Exception instrs"},
{4,"Exception AR instrs"},
{4,"Extend instrs"},
{4,"IfThen instrs"},
{4,"Immediate instrs"},
{4,"Interwork instrs"},
{4,"Jazelle instrs"},
{}
}

Definiert in Zeile 154 der Datei cpuinfo_v7.c.

struct cpuinfo_bitfield_desc_s cpuinf_isar2[]
Initialisierung:
= {
{4,"LoadStore instrs"},
{4,"Memhint instrs"},
{4,"MultiAccess Interruptible instructions"},
{4,"Mult instrs"},
{4,"MultS instrs"},
{4,"MultU instrs"},
{4,"PSR AR instrs"},
{4,"Reversal instrs"},
{}
}

Definiert in Zeile 166 der Datei cpuinfo_v7.c.

struct cpuinfo_bitfield_desc_s cpuinf_isar3[]
Initialisierung:
= {
{4,"Saturate instrs"},
{4,"SIMD instrs"},
{4,"SVC instrs"},
{4,"SynchPrim instrs"},
{4,"TabBranch instrs"},
{4,"ThumbCopy instrs"},
{4,"TrueNOP instrs"},
{4,"T2 Exec Env instrs"},
{}
}

Definiert in Zeile 178 der Datei cpuinfo_v7.c.

struct cpuinfo_bitfield_desc_s cpuinf_isar4[]
Initialisierung:
= {
{4,"Unprivileged instrs"},
{4,"WithShifts instrs"},
{4,"Writeback instrs"},
{4,"SMC instrs"},
{4,"Barrier instrs"},
{4,"SynchPrim_instrs_frac"},
{4,"PSR_M instrs"},
{4,"-"},
{}
}

Definiert in Zeile 190 der Datei cpuinfo_v7.c.

struct cpuinfo_bitfield_desc_s cpuinf_isar5[]
Initialisierung:
= {
{32,"-"},
{}
}

Definiert in Zeile 202 der Datei cpuinfo_v7.c.

struct cpuinfo_bitfield_desc_s cpuinf_mmfr0[]
Initialisierung:
= {
{4,"VMSA support"},
{4,"PMSA support"},
{4,"Cache coherence"},
{4,"Outer shareable"},
{4,"TCM support"},
{4,"Auxiliary registers"},
{4,"FCSE support"},
{4,"-"},
{}
}

Definiert in Zeile 60 der Datei cpuinfo_v7.c.

struct cpuinfo_bitfield_desc_s cpuinf_mmfr1[]
Initialisierung:
= {
{4,"L1 Harvard cache VA"},
{4,"L1 unified cache VA"},
{4,"L1 Harvard cache s/w"},
{4,"L1 unified cache s/w"},
{4,"L1 Harvard cache"},
{4,"L1 unified cache"},
{4,"L1 cache test & clean"},
{4,"Branch predictor"},
{}
}

Definiert in Zeile 72 der Datei cpuinfo_v7.c.

struct cpuinfo_bitfield_desc_s cpuinf_mmfr2[]
Initialisierung:
= {
{4,"L1 Harvard fg prefetch"},
{4,"L1 Harvard bg prefetch"},
{4,"L1 Harvard range"},
{4,"Harvard TLB"},
{4,"Unified TLB"},
{4,"Mem barrier"},
{4,"WFI stall"},
{4,"HW access flag"},
{}
}

Definiert in Zeile 84 der Datei cpuinfo_v7.c.

struct cpuinfo_bitfield_desc_s cpuinf_mmfr3[]
Initialisierung:
= {
{4,"Cache maintain MVA", mmfr3_cache},
{4,"Cache maintain set/way", mmfr3_cache},
{4,"Branch predictor maintenance", mmfr3_bp},
{4,"Maintenance broadcast"},
{4,"-"},
{4,"Transl. table coherent walk"},
{4,"Cached memory size", mmfr3_cms},
{4,"Supersection support", mmfr3_ss},
{}
}

Definiert in Zeile 130 der Datei cpuinfo_v7.c.

struct cpuinfo_bitfield_desc_s cpuinf_mpubase[]
Initialisierung:
= {
{32,"Base address"},
{}
}

Definiert in Zeile 301 der Datei cpuinfo_v7.c.

struct cpuinfo_bitfield_desc_s cpuinf_mpusizeen[]
Initialisierung:
= {
{1,"Enabled"},
{5,"Size", mpu_region_size_str},
{2,"-"},
{8,"Sub-regions disabled", bitfield8},
{}
}

Definiert in Zeile 352 der Datei cpuinfo_v7.c.

struct cpuinfo_bitfield_desc_s cpuinf_mputype[]
Initialisierung:
= {
{1,"S"},
{7,"-"},
{8,"Num of MPU regions"},
{}
}

Definiert in Zeile 294 der Datei cpuinfo_v7.c.

struct cpuinfo_bitfield_desc_s cpuinf_sctlr[]
Initialisierung:
= {
{1,"MPU Enable"},
{1,"Strict Align"},
{1,"L1 DCache Enable"},
{4,"- (SBO)"},
{4,"- (SBZ)"},
{1,"Branch Pred Enable"},
{1,"L1 ICache Enable"},
{1,"High Vector"},
{1,"Round Robin"},
{1,"- (SBZ)"},
{1,"- (SBO)"},
{1,"MPU background reg"},
{1,"- (SBO)"},
{1,"Div0 exception"},
{1,"- (SBZ)"},
{1,"FIQ Enable"},
{2,"- (SBO)"},
{1,"VIC"},
{1,"CPSR E bit"},
{1,"- (SBZ)"},
{1,"NMFI"},
{1,"TRE"},
{1,"AFE"},
{1,"Thumb exceptions"},
{1,"Endian"},
{}
}

Definiert in Zeile 306 der Datei cpuinfo_v7.c.

struct cpuinfo_bitfield_desc_s cpuinf_sctlr_vmsa[]
Initialisierung:
= {
{1,"MMU Enable"},
{1,"Strict Align"},
{1,"Data or Unified Cache Enable"},
{1,"CP15 Barrier Enable"},
{3,"- (SBO)"},
{3,"- (SBZ)"},
{1,"SWP/SWPB Enable"},
{1,"Branch Pred Enable"},
{1,"ICache Enable"},
{1,"High Vector"},
{1,"Round Robin"},
{1,"- (SBZ)"},
{1,"- (SBO)"},
{1,"HA flag"},
{1,"- (SBO)"},
{1,"WXN (virt. ext. only)"},
{1,"UWXN (virt. ext. only)"},
{1,"FIQ Enable"},
{2,"- (SBO)"},
{1,"VE"},
{1,"CPSR E"},
{1,"- (SBZ)"},
{1,"NMFI"},
{1,"TRE"},
{1,"AFE"},
{1,"Thumb exceptions"},
{1,"- (SBZ)"},
{}
}

Definiert in Zeile 840 der Datei cpuinfo_v7.c.

struct cpuinfo_bitfield_desc_s cpuinf_tcmreg[]
Initialisierung:
= {
{1,"Enabled"},
{1,"-"},
{5,"Size", cache_tcm_size_str},
{5,"-"},
{20,"Base address", cache_tcm_addr_str},
{}
}

Definiert in Zeile 285 der Datei cpuinfo_v7.c.

struct cpuinfo_bitfield_desc_s cpuinf_tlbtype[]
Initialisierung:
= {
{1,"TLB", tlb_unified},
{2,"TLB entries", tlb_entries},
{5,"-"},
{8,"Lockable unified or data entries"},
{8,"Lockable instruction entries"},
{8,"(zero)"},
{}
}

Definiert in Zeile 830 der Datei cpuinfo_v7.c.

struct cpuinfo_bitfield_desc_s cpuinf_ttbcr[]
Initialisierung:
= {
{3,"N", ttbcr_n },
{1,"(zero)" },
{1,"TTBR0 walks disabled" },
{1,"TTBR1 walks disabled" },
{25,"(zero)" },
{1,"Long descriptors" },
{}
}

Definiert in Zeile 904 der Datei cpuinfo_v7.c.

struct cpuinfo_bitfield_desc_s cpuinf_ttbr0[]
Initialisierung:
= {
{1,"IRGN[1]"},
{1,"Shareable" },
{1,"(impl. defined)" },
{2,"RGN (Outer cacheability)" },
{1,"NOS (Inner shareable)" },
{1,"IRGN[0]" },
{25,"Table address", ttbraddr0 },
{}
}

Definiert in Zeile 914 der Datei cpuinfo_v7.c.

struct cpuinfo_bitfield_desc_s cpuinf_ttbr1[]
Initialisierung:
= {
{1,"IRGN[1]"},
{1,"Shareable" },
{1,"(impl. defined)" },
{2,"RGN (Outer cacheability)" },
{1,"NOS (Inner shareable)" },
{1,"IRGN[0]" },
{25,"Table address", ttbraddr1 },
{}
}

Definiert in Zeile 925 der Datei cpuinfo_v7.c.

struct cpuinfo_word_desc_s cpuinfo_desc_pmsa[]

Definiert in Zeile 473 der Datei cpuinfo_v7.c.

struct cpuinfo_word_desc_s cpuinfo_desc_vmsa[]

Definiert in Zeile 960 der Datei cpuinfo_v7.c.

const char* csvhead = "Virt.addr,Table,Type,P bit,NG bit,Domain,Phys.addr,L2 ref,S bit,Privileged/Nonpriv.,Caching,Memtype,XN bit\n"

Definiert in Zeile 1427 der Datei cpuinfo_v7.c.

char linebuf[256]
static

Definiert in Zeile 3 der Datei cpuinfo_v7.c.

const char* two_nth_str[]
static
Initialisierung:
= {
"1", "2", "4", "8", "16", "32", "64", "128", "256", "512", "1K", "2K", "4K", "8K", "16K", "32K"
}

Definiert in Zeile 5 der Datei cpuinfo_v7.c.