This source file includes following definitions.
- filewritetask
- sub_FFACC030_my
- sub_FFACC170_my
- sub_FFACBBE4_my
1
2
3
4 #include "lolevel.h"
5 #include "platform.h"
6
7 typedef struct {
8 unsigned int address;
9 unsigned int length;
10 } cam_ptp_data_chunk;
11
12 #define MAX_CHUNKS_FOR_FWT 7
13
14
15
16
17
18
19 typedef struct
20 {
21 int unkn1[5];
22 cam_ptp_data_chunk pdc[MAX_CHUNKS_FOR_FWT];
23 int unkn2;
24 char name[32];
25 } fwt_data_struct;
26
27 #include "../../../generic/filewrite.c"
28
29
30
31 void __attribute__((naked,noinline)) filewritetask() {
32 asm volatile (
33 " STMFD SP!, {R1-R5,LR} \n"
34 " LDR R4, =0xC950 \n"
35
36 "loc_FFACBD60:\n"
37 " LDR R0, [R4, #0x10] \n"
38 " MOV R2, #0 \n"
39 " ADD R1, SP, #8 \n"
40 " BL sub_FF83A4C8 /*_ReceiveMessageQueue*/ \n"
41 " CMP R0, #0 \n"
42 " LDRNE R1, =0x33F \n"
43 " LDRNE R0, =0xFFACBE48 /*'dwFWrite.c'*/ \n"
44 " BLNE _DebugAssert \n"
45 " LDR R0, [SP, #8] \n"
46 " LDR R1, [R0] \n"
47 " CMP R1, #9 \n"
48 " ADDLS PC, PC, R1, LSL#2 \n"
49 " B loc_FFACBD60 \n"
50 " B loc_FFACBE28 \n"
51 " B loc_FFACBE28 \n"
52 " B loc_FFACBE28 \n"
53 " B loc_FFACBE28 \n"
54 " B loc_FFACBE28 \n"
55 " B loc_FFACBE28 \n"
56 " B loc_FFACBE28 \n"
57 " B loc_FFACBE30 \n"
58 " B loc_FFACBDBC \n"
59 " B loc_FFACBE20 \n"
60
61 "loc_FFACBDBC:\n"
62 " MOV R0, #0 \n"
63 " STR R0, [SP] \n"
64
65 "loc_FFACBDC4:\n"
66 " LDR R0, [R4, #0x10] \n"
67 " MOV R1, SP \n"
68 " BL sub_FF83A70C /*_GetNumberOfPostedMessages*/ \n"
69 " LDR R0, [SP] \n"
70 " CMP R0, #0 \n"
71 " BEQ loc_FFACBDF0 \n"
72 " LDR R0, [R4, #0x10] \n"
73 " MOV R2, #0 \n"
74 " ADD R1, SP, #4 \n"
75 " BL sub_FF83A4C8 /*_ReceiveMessageQueue*/ \n"
76 " B loc_FFACBDC4 \n"
77
78 "loc_FFACBDF0:\n"
79 " LDR R0, [R4, #4] \n"
80 " CMN R0, #1 \n"
81 " BEQ loc_FFACBE14 \n"
82 " BL fwt_close \n"
83 " MVN R0, #0 \n"
84 " STR R0, [R4, #4] \n"
85 " LDR R0, =0x110BB0 \n"
86 " BL sub_FF877438 \n"
87 " BL sub_FF875694 \n"
88
89 "loc_FFACBE14:\n"
90 " LDR R0, [R4, #0xC] \n"
91 " BL _GiveSemaphore \n"
92 " B loc_FFACBD60 \n"
93
94 "loc_FFACBE20:\n"
95 " BL sub_FFACC030_my \n"
96 " B loc_FFACBD60 \n"
97
98 "loc_FFACBE28:\n"
99 " BL sub_FFACC170_my \n"
100 " B loc_FFACBD60 \n"
101
102 "loc_FFACBE30:\n"
103 " BL sub_FFACBBE4_my \n"
104 " B loc_FFACBD60 \n"
105 );
106 }
107
108
109
110 void __attribute__((naked,noinline)) sub_FFACC030_my() {
111 asm volatile (
112 " STMFD SP!, {R4-R8,LR} \n"
113 " MOV R4, R0 \n"
114 " ADD R0, R0, #0x50 \n"
115 " SUB SP, SP, #0x38 \n"
116 " BL sub_FF877438 \n"
117 " MOV R1, #0 \n"
118 " BL sub_FF87562C \n"
119 " LDR R0, [R4, #0xC] \n"
120 " BL sub_FF810338 \n"
121 " LDR R0, [R4, #0x4C] \n"
122 " LDR R8, =0x1B6 \n"
123 " CMP R0, #1 \n"
124 " LDREQ R0, [R4, #8] \n"
125 " ADD R6, R4, #0x50 \n"
126 " ORREQ R0, R0, #0x8000 \n"
127 " STREQ R0, [R4, #8] \n"
128 " LDR R7, [R4, #8] \n"
129 " LDR R5, [R4, #0xC] \n"
130
131 " STMFD SP!, {R4-R12,LR} \n"
132 " MOV R0, R4 \n"
133 " BL filewrite_main_hook \n"
134 " LDMFD SP!, {R4-R12,LR} \n"
135
136 " MOV R0, R6 \n"
137 " MOV R2, R8 \n"
138 " MOV R1, R7 \n"
139 " BL fwt_open \n"
140 " CMN R0, #1 \n"
141 " BNE sub_FFACC0E8 \n"
142 " MOV R0, R6 \n"
143 " BL sub_FF837470 \n"
144 " MOV R2, #0xF \n"
145 " MOV R1, R6 \n"
146 " MOV R0, SP \n"
147 " BL sub_FFB92348 \n"
148 " LDR R0, =0x41FF \n"
149 " MOV R1, #0 \n"
150 " STRB R1, [SP, #0xF] \n"
151 " STR R0, [SP, #0x20] \n"
152 " MOV R0, #0x10 \n"
153 " ADD R2, SP, #0x24 \n"
154 " STMIA R2, {R0,R1,R5} \n"
155 " ADD R1, SP, #0x20 \n"
156 " MOV R0, SP \n"
157 " STR R5, [SP, #0x30] \n"
158 " STR R5, [SP, #0x34] \n"
159 " BL sub_FF874F9C \n"
160 " MOV R2, R8 \n"
161 " MOV R1, R7 \n"
162 " MOV R0, R6 \n"
163 " BL fwt_open \n"
164 " LDR PC, =0xFFACC0E8 \n"
165 );
166 }
167
168
169
170 void __attribute__((naked,noinline)) sub_FFACC170_my() {
171 asm volatile (
172 " STMFD SP!, {R4-R10,LR} \n"
173 " MOV R5, R0 \n"
174 " LDR R0, [R0] \n"
175 " CMP R0, #6 \n"
176 " BHI loc_FFACC1A4 \n"
177 " ADD R0, R5, R0, LSL#3 \n"
178 " LDR R7, [R0, #0x14]! \n"
179 " LDR R6, [R0, #4] \n"
180 " CMP R6, #0 \n"
181 " BNE loc_FFACC1B4 \n"
182
183 "loc_FFACC198:\n"
184 " MOV R1, R5 \n"
185 " MOV R0, #7 \n"
186 " B sub_FFACC248 \n"
187
188 "loc_FFACC1A4:\n"
189 " LDR R1, =0x299 \n"
190 " LDR R0, =0xFFACBE48 /*'dwFWrite.c'*/ \n"
191 " BL _DebugAssert \n"
192 " B loc_FFACC198 \n"
193
194 "loc_FFACC1B4:\n"
195 " LDR R9, =0xC950 \n"
196 " MOV R4, R6 \n"
197
198 "loc_FFACC1BC:\n"
199 " LDR R0, [R5, #4] \n"
200 " CMP R4, #0x1000000 \n"
201 " MOVLS R8, R4 \n"
202 " MOVHI R8, #0x1000000 \n"
203 " BIC R1, R0, #0xFF000000 \n"
204 " CMP R1, #0 \n"
205 " BICNE R0, R0, #0xFF000000 \n"
206 " RSBNE R0, R0, #0x1000000 \n"
207 " CMPNE R8, R0 \n"
208 " MOVHI R8, R0 \n"
209 " LDR R0, [R9, #4] \n"
210 " MOV R2, R8 \n"
211 " MOV R1, R7 \n"
212 " BL fwt_write \n"
213 " LDR R1, [R5, #4] \n"
214 " CMP R8, R0 \n"
215 " ADD R1, R1, R0 \n"
216 " STR R1, [R5, #4] \n"
217 " BEQ loc_FFACC21C \n"
218 " CMN R0, #1 \n"
219 " LDRNE R0, =0x9200015 \n"
220 " LDREQ R0, =0x9200005 \n"
221 " STR R0, [R5, #0x10] \n"
222 " B loc_FFACC198 \n"
223
224 "loc_FFACC21C:\n"
225 " SUB R4, R4, R0 \n"
226 " CMP R4, R6 \n"
227 " ADD R7, R7, R0 \n"
228 " LDRCS R0, =0xFFACBE48 /*'dwFWrite.c'*/ \n"
229 " MOVCS R1, #0x2C4 \n"
230 " BLCS _DebugAssert \n"
231 " CMP R4, #0 \n"
232 " BNE loc_FFACC1BC \n"
233 " LDR PC, =0xFFACC23C \n"
234 );
235 }
236
237
238
239 void __attribute__((naked,noinline)) sub_FFACBBE4_my() {
240 asm volatile (
241 " STMFD SP!, {R4-R6,LR} \n"
242 " LDR R5, =0xC950 \n"
243 " MOV R4, R0 \n"
244 " LDR R0, [R5, #4] \n"
245 " SUB SP, SP, #0x38 \n"
246 " CMN R0, #1 \n"
247 " BEQ sub_FFACBC2C \n"
248 " LDR R1, [R4, #8] \n"
249 " LDR R6, =0x9200003 \n"
250 " TST R1, #0x8000 \n"
251 " BEQ loc_FFACBC18 \n"
252
253 " LDR R3, =current_write_ignored\n"
254 " LDR R3, [R3]\n"
255 " CMP R3, #0\n"
256 " BNE loc_D\n"
257
258 " BL sub_FF8746D8 \n"
259 " B sub_FFACBC1C \n"
260
261 "loc_FFACBC18:\n"
262 "loc_D:\n"
263 " BL fwt_close \n"
264 " LDR PC, =0xFFACBC1C \n"
265 );
266 }