This source file includes following definitions.
- set_quality
- change_video_tables
- movie_record_task
1 #include "conf.h"
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10
11 void set_quality (int *x)
12 {
13 if (conf.video_mode)
14 *x = 12 - ((conf.video_quality-1) * (12+17) / (99-1));
15 }
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17
18
19
20
21 void change_video_tables(__attribute__ ((unused))int a, __attribute__ ((unused))int b) {}
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25
26
27 void __attribute__((naked,noinline)) movie_record_task()
28 {
29
30 asm volatile (
31 " STMFD SP!, {R2-R10,LR} \n"
32 " LDR R6, =0xFF985FB0\n"
33 " LDR R7, =0xFF9864C0 \n"
34 " LDR R4, =0x6E80 \n"
35 " LDR R9, =0x6C7 \n"
36 " LDR R10, =0x2710 \n"
37 " MOV R8, #1 \n"
38 " MOV R5, #0 \n"
39 "loc_FF986AA4:\n"
40 " LDR R0, [R4, #0x24] \n"
41 " MOV R2, #0 \n"
42 " ADD R1, SP, #4 \n"
43 " BL sub_FF83A27C \n"
44 " LDR R0, [R4, #0x2C] \n"
45 " CMP R0, #0 \n"
46 " LDRNE R0, [R4, #0xC] \n"
47 " CMPNE R0, #2 \n"
48 " LDRNE R0, [R4, #0x44] \n"
49 " CMPNE R0, #6 \n"
50 " BNE loc_FF986BC8 \n"
51 " LDR R0, [SP, #4] \n"
52 " LDR R1, [R0] \n"
53 " SUB R1, R1, #2 \n"
54 " CMP R1, #0xB \n"
55 " ADDCC PC, PC, R1, LSL #2 \n"
56 " B loc_FF986BC8 \n"
57 " B loc_FF986B78 \n"
58 " B loc_FF986B9C \n"
59 " B loc_FF986BAC \n"
60 " B loc_FF986BB4 \n"
61 " B loc_FF986B80 \n"
62 " B loc_FF986BBC \n"
63 " B loc_FF986B8C \n"
64 " B loc_FF986BC8 \n"
65 " B loc_FF986BC4 \n"
66 " B loc_FF986B44 \n"
67 " B loc_FF986B14 \n"
68 "loc_FF986B14:\n"
69
70 " STR R5, [R4, #0x40] \n"
71 " STR R5, [R4, #0x30] \n"
72 " STR R5, [R4, #0x34] \n"
73 " STRH R5, [R4, #6] \n"
74 " STR R6, [R4, #0xB4] \n"
75 " STR R7, [R4, #0xD0] \n"
76 " LDR R0, [R4, #0xC] \n"
77 " ADD R0, R0, #1 \n"
78 " STR R0, [R4, #0xC] \n"
79 " MOV R0, #6 \n"
80 " STR R0, [R4, #0x44] \n"
81 " B loc_FF986B64 \n"
82 "loc_FF986B44:\n"
83
84 " STR R5, [R4, #0x40] \n"
85 " STR R5, [R4, #0x30] \n"
86 " STR R6, [R4, #0xB4] \n"
87 " STR R7, [R4, #0xD0] \n"
88 " LDR R0, [R4, #0xC] \n"
89 " ADD R0, R0, #1 \n"
90 " STR R0, [R4, #0xC] \n"
91 " STR R8, [R4, #0x44] \n"
92 "loc_FF986B64:\n"
93 " LDR R2, =0xFF985790 \n"
94 " LDR R1, =0xB3218 \n"
95 " LDR R0, =0xFF9858A4 \n"
96 " BL sub_FF8540E4 \n"
97 " B loc_FF986BC8 \n"
98 "loc_FF986B78:\n"
99
100 " BL sub_FF986110 \n"
101 " B loc_FF986BC8 \n"
102 "loc_FF986B80:\n"
103
104 " LDR R1, [R4, #0xD0] \n"
105 " BLX R1 \n"
106
107 " LDR R0, =0x6F04 \n"
108 " BL set_quality \n"
109
110 " B loc_FF986BC8 \n"
111 "loc_FF986B8C:\n"
112
113 " LDR R1, [R0, #0x18] \n"
114 " LDR R0, [R0, #4] \n"
115 " BL sub_FFAD9FE8 \n"
116 " B loc_FF986BC8 \n"
117 "loc_FF986B9C:\n"
118
119 " LDR R0, [R4, #0x44] \n"
120 " CMP R0, #5 \n"
121 " STRNE R8, [R4, #0x34] \n"
122 " B loc_FF986BC8 \n"
123 "loc_FF986BAC:\n"
124
125 " BL sub_FF985C40 \n"
126 " B loc_FF986BC8 \n"
127 "loc_FF986BB4:\n"
128
129 " BL sub_FF9858F0 \n"
130 " B loc_FF986BC8 \n"
131 "loc_FF986BBC:\n"
132
133 " BL sub_FF98571C \n"
134 " B loc_FF986BC8 \n"
135 "loc_FF986BC4:\n"
136
137 " BL sub_FF987028 \n"
138 "loc_FF986BC8:\n"
139
140
141 " LDR R1, [SP, #4] \n"
142 " LDR R3, =0xFF985558 \n"
143 " STR R5, [R1] \n"
144 " STR R9, [SP] \n"
145 " LDR R0, [R4, #0x28] \n"
146 " MOV R2, R10 \n"
147 " BL sub_FF83ABF4 \n"
148 " B loc_FF986AA4 \n"
149 );
150 }