root/platform/ixus960_sd950/sub/100d/boot.c

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DEFINITIONS

This source file includes following definitions.
  1. CreateTask_spytask
  2. taskCreateHook
  3. boot
  4. sub_FF8101A4_my
  5. sub_FF810FB8_my
  6. uHwSetup_my
  7. CreateTask_Startup_my
  8. task_Startup_my
  9. taskcreatePhySw_my
  10. init_file_modules_task
  11. sub_FF86A0B0_my
  12. sub_FF84D658_my
  13. sub_FF84D494_my
  14. sub_FF84D32C_my
  15. my_touchw_task

   1 /*
   2  * boot.c - auto-generated by CHDK code_gen.
   3  */
   4 #include "lolevel.h"
   5 #include "platform.h"
   6 #include "core.h"
   7 
   8 const char * const new_sa = &_end;
   9 
  10 /*----------------------------------------------------------------------
  11     CreateTask_spytask
  12 -----------------------------------------------------------------------*/
  13 void CreateTask_spytask() {
  14         _CreateTask("SpyTask", 0x19, 0x2000, core_spytask, 0);
  15 };
  16 
  17 
  18 
  19 void my_touchw_task(void);
  20 
  21 void taskCreateHook(int *p) {
  22     p-=16;
  23     if (p[0]==0xff85c038)  p[0]=(int)capt_seq_task;
  24     if (p[0]==0xff8af7b0)  p[0]=(int)exp_drv_task;
  25     if (p[0]==0xff8584ec)  p[0]=(int)movie_record_task;
  26     if (p[0]==0xffa082a4)  p[0]=(int)filewritetask;
  27     if (p[0]==0xff871070)  p[0]=(int)init_file_modules_task;
  28     if (p[0]==0xff8e85f8)  p[0]=(int)my_touchw_task;
  29 }
  30 
  31 void boot()
  32 {
  33     long *canon_data_src = (void*)0xFFAFB86C;
  34     long *canon_data_dst = (void*)0x1900;
  35     long canon_data_len = 0x137A8 - 0x1900; // data_end - data_start
  36     long *canon_bss_start = (void*)0x137A8; // just after data 
  37     long canon_bss_len = 0xA6234 - 0x137A8; 
  38 
  39     long i;
  40 
  41 
  42     // Enable CPU caches and MPU
  43     asm volatile (
  44     "MRC     p15, 0, R0,c1,c0\n"
  45     "ORR     R0, R0, #0x1000\n"
  46     "ORR     R0, R0, #4\n"
  47     "ORR     R0, R0, #1\n"
  48     "MCR     p15, 0, R0,c1,c0\n"
  49     :::"r0");
  50 
  51     for(i=0;i<canon_data_len/4;i++)
  52     canon_data_dst[i]=canon_data_src[i];
  53 
  54     for(i=0;i<canon_bss_len/4;i++)
  55     canon_bss_start[i]=0;
  56 
  57     // jump to init-sequence that follows the data-copy-routine
  58     asm volatile ("B      sub_FF8101A4_my\n");
  59 };
  60 
  61 
  62 /*************************************************************/
  63 //** sub_FF8101A4_my @ 0xFF8101A4 - 0xFF81020C, length=27
  64 void __attribute__((naked,noinline)) sub_FF8101A4_my() {
  65     //http://chdk.setepontos.com/index.php/topic,4194.0.html
  66     *(int*)0x1930=(int)taskCreateHook;
  67 
  68     // replacement of sub_FF844050 for correct power-on.
  69     //(short press = playback mode, long press = record mode)
  70     *(int*)(0x23E8+0x4)= (*(int*)0xC0220078) & 1 ? 0x200000 : 0x400000;
  71     
  72 asm volatile (
  73 "    LDR     R0, =0xFF81021C \n"
  74 "    MOV     R1, #0 \n"
  75 "    LDR     R3, =0xFF810254 \n"
  76 
  77 "loc_FF8101B0:\n"
  78 "    CMP     R0, R3 \n"
  79 "    LDRCC   R2, [R0], #4 \n"
  80 "    STRCC   R2, [R1], #4 \n"
  81 "    BCC     loc_FF8101B0 \n"
  82 "    LDR     R0, =0xFF810254 \n"
  83 "    MOV     R1, #0x4B0 \n"
  84 "    LDR     R3, =0xFF810468 \n"
  85 
  86 "loc_FF8101CC:\n"
  87 "    CMP     R0, R3 \n"
  88 "    LDRCC   R2, [R0], #4 \n"
  89 "    STRCC   R2, [R1], #4 \n"
  90 "    BCC     loc_FF8101CC \n"
  91 "    MOV     R0, #0xD2 \n"
  92 "    MSR     CPSR_cxsf, R0 \n"
  93 "    MOV     SP, #0x1000 \n"
  94 "    MOV     R0, #0xD3 \n"
  95 "    MSR     CPSR_cxsf, R0 \n"
  96 "    MOV     SP, #0x1000 \n"
  97 "    LDR     R0, =0x6C4 \n"
  98 "    LDR     R2, =0xEEEEEEEE \n"
  99 "    MOV     R3, #0x1000 \n"
 100 
 101 "loc_FF810200:\n"
 102 "    CMP     R0, R3 \n"
 103 "    STRCC   R2, [R0], #4 \n"
 104 "    BCC     loc_FF810200 \n"
 105 "    BL      sub_FF810FB8_my \n"  // --> Patched. Old value = 0xFF810FB8.
 106 );
 107 }
 108 
 109 /*************************************************************/
 110 //** sub_FF810FB8_my @ 0xFF810FB8 - 0xFF811058, length=41
 111 void __attribute__((naked,noinline)) sub_FF810FB8_my() {
 112 asm volatile (
 113 "    STR     LR, [SP, #-4]! \n"
 114 "    SUB     SP, SP, #0x74 \n"
 115 "    MOV     R0, SP \n"
 116 "    MOV     R1, #0x74 \n"
 117 "    BL      sub_FFA91C1C \n"
 118 "    MOV     R0, #0x53000 \n"
 119 "    STR     R0, [SP, #4] \n"
 120 
 121 #if defined(CHDK_NOT_IN_CANON_HEAP) // use original heap offset if CHDK is loaded in high memory
 122 "    LDR     R0, =0xA6234 \n"
 123 #else
 124 "    LDR     R0, =new_sa\n"   // otherwise use patched value
 125 "    LDR     R0, [R0]\n"      //
 126 #endif
 127 
 128 "    LDR     R2, =0x2ABC00 \n"
 129 "    LDR     R1, =0x2A4968 \n"
 130 "    STR     R0, [SP, #8] \n"
 131 "    SUB     R0, R1, R0 \n"
 132 "    ADD     R3, SP, #0xC \n"
 133 "    STR     R2, [SP] \n"
 134 "    STMIA   R3, {R0-R2} \n"
 135 "    MOV     R0, #0x22 \n"
 136 "    STR     R0, [SP, #0x18] \n"
 137 "    MOV     R0, #0x68 \n"
 138 "    STR     R0, [SP, #0x1C] \n"
 139 "    LDR     R0, =0x19B \n"
 140 "    MOV     R1, #0x64 \n"
 141 "    STRD    R0, [SP, #0x20] \n"
 142 "    MOV     R0, #0x78 \n"
 143 "    STRD    R0, [SP, #0x28] \n"
 144 "    MOV     R0, #0 \n"
 145 "    STR     R0, [SP, #0x30] \n"
 146 "    STR     R0, [SP, #0x34] \n"
 147 "    MOV     R0, #0x10 \n"
 148 "    STR     R0, [SP, #0x5C] \n"
 149 "    MOV     R0, #0x800 \n"
 150 "    STR     R0, [SP, #0x60] \n"
 151 "    MOV     R0, #0xA0 \n"
 152 "    STR     R0, [SP, #0x64] \n"
 153 "    MOV     R0, #0x280 \n"
 154 "    STR     R0, [SP, #0x68] \n"
 155 "    LDR     R1, =uHwSetup_my \n"  // --> Patched. Old value = 0xFF814DBC.
 156 "    MOV     R0, SP \n"
 157 "    MOV     R2, #0 \n"
 158 "    BL      sub_FF812D70 \n"
 159 "    ADD     SP, SP, #0x74 \n"
 160 "    LDR     PC, [SP], #4 \n"
 161 );
 162 }
 163 
 164 /*************************************************************/
 165 //** uHwSetup_my @ 0xFF814DBC - 0xFF814E30, length=30
 166 void __attribute__((naked,noinline)) uHwSetup_my() {
 167 asm volatile (
 168 "    STMFD   SP!, {R4,LR} \n"
 169 "    BL      sub_FF81095C \n"
 170 "    BL      sub_FF819948 \n"
 171 "    CMP     R0, #0 \n"
 172 "    LDRLT   R0, =0xFF814ED0 /*'dmSetup'*/ \n"
 173 "    BLLT    _err_init_task \n"
 174 "    BL      sub_FF8149E0 \n"
 175 "    CMP     R0, #0 \n"
 176 "    LDRLT   R0, =0xFF814ED8 /*'termDriverInit'*/ \n"
 177 "    BLLT    _err_init_task \n"
 178 "    LDR     R0, =0xFF814EE8 /*'/_term'*/ \n"
 179 "    BL      sub_FF814ACC \n"
 180 "    CMP     R0, #0 \n"
 181 "    LDRLT   R0, =0xFF814EF0 /*'termDeviceCreate'*/ \n"
 182 "    BLLT    _err_init_task \n"
 183 "    LDR     R0, =0xFF814EE8 /*'/_term'*/ \n"
 184 "    BL      sub_FF81357C \n"
 185 "    CMP     R0, #0 \n"
 186 "    LDRLT   R0, =0xFF814F04 /*'stdioSetup'*/ \n"
 187 "    BLLT    _err_init_task \n"
 188 "    BL      sub_FF8194D0 \n"
 189 "    CMP     R0, #0 \n"
 190 "    LDRLT   R0, =0xFF814F10 /*'stdlibSetup'*/ \n"
 191 "    BLLT    _err_init_task \n"
 192 "    BL      sub_FF8114D0 \n"
 193 "    CMP     R0, #0 \n"
 194 "    LDRLT   R0, =0xFF814F1C /*'armlib_setup'*/ \n"
 195 "    BLLT    _err_init_task \n"
 196 "    LDMFD   SP!, {R4,LR} \n"
 197 "    B       CreateTask_Startup_my \n"  // --> Patched. Old value = 0xFF81DC0C.
 198 );
 199 }
 200 
 201 /*************************************************************/
 202 //** CreateTask_Startup_my @ 0xFF81DC0C - 0xFF81DC80, length=30
 203 void __attribute__((naked,noinline)) CreateTask_Startup_my() {
 204 asm volatile (
 205 "    STMFD   SP!, {R3,LR} \n"
 206 //"  BL      _sub_FF822DA4 \n"  // --> Nullsub call removed.
 207 "    BL      sub_FF82BA24 \n"
 208 "    CMP     R0, #0 \n"
 209 "    BNE     loc_FF81DC44 \n"
 210 "    LDR     R2, =0xC0220000 \n"
 211 "    LDR     R0, [R2, #0x7C] \n"
 212 "    LDR     R1, [R2, #0x78] \n"
 213 "    AND     R0, R0, R1 \n"
 214 "    TST     R0, #1 \n"
 215 "    BEQ     loc_FF81DC44 \n"
 216 "    MOV     R0, #0x44 \n"
 217 "    STR     R0, [R2, #0x4C] \n"
 218 
 219 "loc_FF81DC40:\n"
 220 "    B       loc_FF81DC40 \n"
 221 
 222 "loc_FF81DC44:\n"
 223 //"  BL      _sub_FF844050 \n"  // Removed for correct power-on
 224 //"  BL      _sub_FF822DA8 \n"  // --> Nullsub call removed.
 225 "    BL      sub_FF8295B0 \n"
 226 "    MOV     R1, #0x300000 \n"
 227 "    MOV     R0, #0 \n"
 228 "    BL      sub_FF8297F8 \n"
 229 "    BL      sub_FF8297A4 \n"
 230 "    MOV     R3, #0 \n"
 231 "    STR     R3, [SP] \n"
 232 "    LDR     R3, =task_Startup_my \n"  // --> Patched. Old value = 0xFF81DBB0.
 233 "    MOV     R2, #0 \n"
 234 "    MOV     R1, #0x19 \n"
 235 "    LDR     R0, =0xFF81DC88 /*'Startup'*/ \n"
 236 "    BL      _CreateTask \n"
 237 "    MOV     R0, #0 \n"
 238 "    LDMFD   SP!, {R12,PC} \n"
 239 );
 240 }
 241 
 242 /*************************************************************/
 243 //** task_Startup_my @ 0xFF81DBB0 - 0xFF81DC08, length=23
 244 void __attribute__((naked,noinline)) task_Startup_my() {
 245 asm volatile (
 246 "    STMFD   SP!, {R4,LR} \n"
 247 "    BL      sub_FF81517C \n"
 248 "    BL      sub_FF823F44 \n"
 249 "    BL      sub_FF820E24 \n"
 250 //"  BL      _sub_FF84465C \n"  // --> Nullsub call removed.
 251 "    BL      sub_FF82BC04 \n"
 252 //"  BL      _sub_FF82BAEC \n"  // load DISKBOOT.BIN
 253 "    BL      CreateTask_spytask\n" // added
 254 "    BL      sub_FF86D5F0 \n"
 255 "    BL      sub_FF82BC54 \n"
 256 "    BL      sub_FF828AF4 \n"
 257 "    BL      sub_FF82BDD0 \n"
 258 "    BL      taskcreatePhySw_my \n"  // --> Patched. Old value = 0xFF822D48. Checks buttons and acts accordingly
 259 "    BL      sub_FF825BD0 \n"
 260 "    BL      sub_FF82BDE8 \n"
 261 //"  BL      _sub_FF820AF8 \n"  // --> Nullsub call removed.
 262 "    BL      sub_FF8220D8 \n"
 263 "    BL      sub_FF82B7D0 \n"
 264 "    BL      sub_FF822874 \n"
 265 "    BL      sub_FF821FE4 \n"
 266 "    BL      sub_FF82C88C \n"
 267 "    BL      sub_FF821FA0 \n"
 268 "    LDMFD   SP!, {R4,LR} \n"
 269 "    B       sub_FF815088 \n"
 270 );
 271 }
 272 
 273 /*************************************************************/
 274 //** taskcreatePhySw_my @ 0xFF822D48 - 0xFF822D7C, length=14
 275 void __attribute__((naked,noinline)) taskcreatePhySw_my() {
 276 asm volatile (
 277 "    STMFD   SP!, {R3-R5,LR} \n"
 278 "    LDR     R4, =0x1C98 \n"
 279 "    LDR     R0, [R4, #0x10] \n"
 280 "    CMP     R0, #0 \n"
 281 "    BNE     loc_FF822D7C \n"
 282 "    MOV     R3, #0 \n"
 283 "    STR     R3, [SP] \n"
 284 "    LDR     R3, =mykbd_task \n"  // --> Patched. Old value = 0xFF822D14.
 285 "    MOV     R2, #0x2000 \n"  // --> Patched. Old value = 0x800. stack size for new task_PhySw so we don't have to do stack switch
 286 "    MOV     R1, #0x17 \n"
 287 "    LDR     R0, =0xFF822F3C /*'PhySw'*/ \n"
 288 "    BL      sub_FF81BDC8 /*_CreateTaskStrictly*/ \n"
 289 "    STR     R0, [R4, #0x10] \n"
 290 
 291 "loc_FF822D7C:\n"
 292 "    LDMFD   SP!, {R3-R5,PC} \n"
 293 );
 294 }
 295 
 296 /*************************************************************/
 297 //** init_file_modules_task @ 0xFF871070 - 0xFF8710A4, length=14
 298 void __attribute__((naked,noinline)) init_file_modules_task() {
 299 asm volatile (
 300 "    STMFD   SP!, {R4-R6,LR} \n"
 301 "    BL      sub_FF86A084 \n"
 302 "    LDR     R5, =0x5006 \n"
 303 "    MOVS    R4, R0 \n"
 304 "    MOVNE   R1, #0 \n"
 305 "    MOVNE   R0, R5 \n"
 306 "    BLNE    _PostLogicalEventToUI \n"
 307 "    BL      sub_FF86A0B0_my \n"  // --> Patched. Old value = 0xFF86A0B0.
 308 "    BL      core_spytask_can_start\n"  // CHDK: Set "it's-safe-to-start" flag for spytask
 309 "    CMP     R4, #0 \n"
 310 "    MOVEQ   R0, R5 \n"
 311 "    LDMEQFD SP!, {R4-R6,LR} \n"
 312 "    MOVEQ   R1, #0 \n"
 313 "    BEQ     _PostLogicalEventToUI \n"
 314 "    LDMFD   SP!, {R4-R6,PC} \n"
 315 );
 316 }
 317 
 318 /*************************************************************/
 319 //** sub_FF86A0B0_my @ 0xFF86A0B0 - 0xFF86A0E8, length=15
 320 void __attribute__((naked,noinline)) sub_FF86A0B0_my() {
 321 asm volatile (
 322 "    STMFD   SP!, {R4,LR} \n"
 323 "    BL      sub_FF84D658_my \n"  // --> Patched. Old value = 0xFF84D658.
 324 "    LDR     R4, =0x58B0 \n"
 325 "    LDR     R0, [R4, #4] \n"
 326 "    CMP     R0, #0 \n"
 327 "    BNE     loc_FF86A0E0 \n"
 328 "    BL      sub_FF87A208 \n"
 329 "    BL      sub_FF8FDA18 \n"
 330 "    BL      sub_FF87A208 \n"
 331 "    BL      sub_FF90A56C \n"
 332 "    BL      sub_FF87A218 \n"
 333 "    BL      sub_FF8FDAC0 \n"
 334 
 335 "loc_FF86A0E0:\n"
 336 "    MOV     R0, #1 \n"
 337 "    STR     R0, [R4] \n"
 338 "    LDMFD   SP!, {R4,PC} \n"
 339 );
 340 }
 341 
 342 /*************************************************************/
 343 //** sub_FF84D658_my @ 0xFF84D658 - 0xFF84D6F0, length=39
 344 void __attribute__((naked,noinline)) sub_FF84D658_my() {
 345 asm volatile (
 346 "    STMFD   SP!, {R4-R6,LR} \n"
 347 "    MOV     R6, #0 \n"
 348 "    MOV     R0, R6 \n"
 349 "    BL      sub_FF84D228 \n"
 350 "    LDR     R4, =0x15F80 \n"
 351 "    MOV     R5, #0 \n"
 352 "    LDR     R0, [R4, #0x38] \n"
 353 "    BL      sub_FF84DBF0 \n"
 354 "    CMP     R0, #0 \n"
 355 "    LDREQ   R0, =0x2B44 \n"
 356 "    STREQ   R5, [R0, #0xC] \n"
 357 "    STREQ   R5, [R0, #0x10] \n"
 358 "    STREQ   R5, [R0, #0x14] \n"
 359 "    MOV     R0, R6 \n"
 360 "    BL      sub_FF84D268 \n"
 361 "    MOV     R0, R6 \n"
 362 "    BL      sub_FF84D494_my \n"  // --> Patched. Old value = 0xFF84D494.
 363 "    MOV     R5, R0 \n"
 364 "    MOV     R0, R6 \n"
 365 "    BL      sub_FF84D500 \n"
 366 "    LDR     R1, [R4, #0x3C] \n"
 367 "    AND     R2, R5, R0 \n"
 368 "    CMP     R1, #0 \n"
 369 "    MOV     R0, #0 \n"
 370 "    MOVEQ   R0, #0x80000001 \n"
 371 "    BEQ     loc_FF84D6EC \n"
 372 "    LDR     R3, [R4, #0x2C] \n"
 373 "    CMP     R3, #2 \n"
 374 "    MOVEQ   R0, #4 \n"
 375 "    CMP     R1, #5 \n"
 376 "    ORRNE   R0, R0, #1 \n"
 377 "    BICEQ   R0, R0, #1 \n"
 378 "    CMP     R2, #0 \n"
 379 "    BICEQ   R0, R0, #2 \n"
 380 "    ORREQ   R0, R0, #0x80000000 \n"
 381 "    BICNE   R0, R0, #0x80000000 \n"
 382 "    ORRNE   R0, R0, #2 \n"
 383 
 384 "loc_FF84D6EC:\n"
 385 "    STR     R0, [R4, #0x40] \n"
 386 "    LDMFD   SP!, {R4-R6,PC} \n"
 387 );
 388 }
 389 
 390 /*************************************************************/
 391 //** sub_FF84D494_my @ 0xFF84D494 - 0xFF84D4FC, length=27
 392 void __attribute__((naked,noinline)) sub_FF84D494_my() {
 393 asm volatile (
 394 "    STMFD   SP!, {R4-R6,LR} \n"
 395 "    LDR     R5, =0x2B44 \n"
 396 "    MOV     R6, R0 \n"
 397 "    LDR     R0, [R5, #0x10] \n"
 398 "    CMP     R0, #0 \n"
 399 "    MOVNE   R0, #1 \n"
 400 "    LDMNEFD SP!, {R4-R6,PC} \n"
 401 "    MOV     R0, #0x17 \n"
 402 "    MUL     R1, R0, R6 \n"
 403 "    LDR     R0, =0x15F80 \n"
 404 "    ADD     R4, R0, R1, LSL#2 \n"
 405 "    LDR     R0, [R4, #0x38] \n"
 406 "    MOV     R1, R6 \n"
 407 "    BL      sub_FF84D32C_my \n"  // --> Patched. Old value = 0xFF84D32C.
 408 "    CMP     R0, #0 \n"
 409 "    LDMEQFD SP!, {R4-R6,PC} \n"
 410 "    LDR     R0, [R4, #0x38] \n"
 411 "    MOV     R1, R6 \n"
 412 "    BL      sub_FF84DD08 \n"
 413 "    CMP     R0, #0 \n"
 414 "    LDMEQFD SP!, {R4-R6,PC} \n"
 415 "    MOV     R0, R6 \n"
 416 "    BL      sub_FF84CE48 \n"
 417 "    CMP     R0, #0 \n"
 418 "    MOVNE   R1, #1 \n"
 419 "    STRNE   R1, [R5, #0x10] \n"
 420 "    LDMFD   SP!, {R4-R6,PC} \n"
 421 );
 422 }
 423 
 424 /*************************************************************/
 425 //** sub_FF84D32C_my @ 0xFF84D32C - 0xFF84D490, length=90
 426 void __attribute__((naked,noinline)) sub_FF84D32C_my() {
 427 asm volatile (
 428 "    STMFD   SP!, {R4-R8,LR} \n"
 429 "    MOV     R8, R0 \n"
 430 "    MOV     R0, #0x17 \n"
 431 "    MUL     R1, R0, R1 \n"
 432 "    LDR     R0, =0x15F80 \n"
 433 "    MOV     R6, #0 \n"
 434 "    ADD     R7, R0, R1, LSL#2 \n"
 435 "    LDR     R0, [R7, #0x3C] \n"
 436 "    MOV     R5, #0 \n"
 437 "    CMP     R0, #6 \n"
 438 "    ADDLS   PC, PC, R0, LSL#2 \n"
 439 "    B       loc_FF84D478 \n"
 440 "    B       loc_FF84D390 \n"
 441 "    B       loc_FF84D378 \n"
 442 "    B       loc_FF84D378 \n"
 443 "    B       loc_FF84D378 \n"
 444 "    B       loc_FF84D378 \n"
 445 "    B       loc_FF84D470 \n"
 446 "    B       loc_FF84D378 \n"
 447 
 448 "loc_FF84D378:\n"
 449 "    MOV     R2, #0 \n"
 450 "    MOV     R1, #0x200 \n"
 451 "    MOV     R0, #3 \n"
 452 "    BL      sub_FF86655C \n"
 453 "    MOVS    R4, R0 \n"
 454 "    BNE     loc_FF84D398 \n"
 455 
 456 "loc_FF84D390:\n"
 457 "    MOV     R0, #0 \n"
 458 "    LDMFD   SP!, {R4-R8,PC} \n"
 459 
 460 "loc_FF84D398:\n"
 461 "    LDR     R12, [R7, #0x4C] \n"
 462 "    MOV     R3, R4 \n"
 463 "    MOV     R2, #1 \n"
 464 "    MOV     R1, #0 \n"
 465 "    MOV     R0, R8 \n"
 466 "    BLX     R12 \n"
 467 "    CMP     R0, #1 \n"
 468 "    BNE     loc_FF84D3C4 \n"
 469 "    MOV     R0, #3 \n"
 470 "    BL      sub_FF86669C \n"
 471 "    B       loc_FF84D390 \n"
 472 
 473 "loc_FF84D3C4:\n"
 474 "    MOV     R0, R8 \n"
 475 "    BL      sub_FF91AD24 \n"
 476 
 477 "    MOV     R1, R4\n"              //  pointer to MBR in R1
 478 "    BL      mbr_read_dryos\n"      //  total sectors count in R0 before and after call
 479 
 480 // Start of DataGhost's FAT32 autodetection code
 481 // Policy: If there is a partition which has type W95 FAT32, use the first one of those for image storage
 482 // According to the code below, we can use R1, R2, R3 and R12.
 483 // LR wasn't really used anywhere but for storing a part of the partition signature. This is the only thing
 484 // that won't work with an offset, but since we can load from LR+offset into LR, we can use this to do that :)
 485 "    MOV     R12, R4\n"             // Copy the MBR start address so we have something to work with
 486 "    MOV     LR, R4\n"              // Save old offset for MBR signature
 487 "    MOV     R1, #1\n"              // Note the current partition number
 488 "    B       dg_sd_fat32_enter\n"   // We actually need to check the first partition as well, no increments yet!
 489 "dg_sd_fat32:\n"
 490 "    CMP     R1, #4\n"              // Did we already see the 4th partition?
 491 "    BEQ     dg_sd_fat32_end\n"     // Yes, break. We didn't find anything, so don't change anything.
 492 "    ADD     R12, R12, #0x10\n"     // Second partition
 493 "    ADD     R1, R1, #1\n"          // Second partition for the loop
 494 "dg_sd_fat32_enter:\n"
 495 "    LDRB    R2, [R12, #0x1BE]\n"   // Partition status
 496 "    LDRB    R3, [R12, #0x1C2]\n"   // Partition type (FAT32 = 0xB)
 497 "    CMP     R3, #0xB\n"            // Is this a FAT32 partition?
 498 "    CMPNE   R3, #0xC\n"            // Not 0xB, is it 0xC (FAT32 LBA) then?
 499 "    CMPNE   R3, #0x7\n"            // exFat?
 500 "    BNE     dg_sd_fat32\n"         // No, it isn't. Loop again.
 501 "    CMP     R2, #0x00\n"           // It is, check the validity of the partition type
 502 "    CMPNE   R2, #0x80\n"
 503 "    BNE     dg_sd_fat32\n"         // Invalid, go to next partition
 504                                     // This partition is valid, it's the first one, bingo!
 505 "    MOV     R4, R12\n"             // Move the new MBR offset for the partition detection.
 506 
 507 "dg_sd_fat32_end:\n"
 508 // End of DataGhost's FAT32 autodetection code
 509 
 510 "    LDRB    R1, [R4, #0x1C9] \n"
 511 "    LDRB    R3, [R4, #0x1C8] \n"
 512 "    LDRB    R12, [R4, #0x1CC] \n"
 513 "    MOV     R1, R1, LSL#24 \n"
 514 "    ORR     R1, R1, R3, LSL#16 \n"
 515 "    LDRB    R3, [R4, #0x1C7] \n"
 516 "    LDRB    R2, [R4, #0x1BE] \n"
 517 //"  LDRB    LR, [R4, #0x1FF] \n"
 518 "    ORR     R1, R1, R3, LSL#8 \n"
 519 "    LDRB    R3, [R4, #0x1C6] \n"
 520 "    CMP     R2, #0 \n"
 521 "    CMPNE   R2, #0x80 \n"
 522 "    ORR     R1, R1, R3 \n"
 523 "    LDRB    R3, [R4, #0x1CD] \n"
 524 "    MOV     R3, R3, LSL#24 \n"
 525 "    ORR     R3, R3, R12, LSL#16 \n"
 526 "    LDRB    R12, [R4, #0x1CB] \n"
 527 "    ORR     R3, R3, R12, LSL#8 \n"
 528 "    LDRB    R12, [R4, #0x1CA] \n"
 529 "    ORR     R3, R3, R12 \n"
 530 //"  LDRB    R12, [R4, #0x1FE] \n"  // Replaced, see below
 531 //mod start
 532 "    LDRB    R12, [LR,#0x1FE]\n"           // New! First MBR signature byte (0x55)
 533 "    LDRB    LR, [LR,#0x1FF]\n"            //      Last MBR signature byte (0xAA)
 534 //mod end
 535 "    MOV     R4, #0 \n"
 536 "    BNE     loc_FF84D44C \n"
 537 "    CMP     R0, R1 \n"
 538 "    BCC     loc_FF84D44C \n"
 539 "    ADD     R2, R1, R3 \n"
 540 "    CMP     R2, R0 \n"
 541 "    CMPLS   R12, #0x55 \n"
 542 "    CMPEQ   LR, #0xAA \n"
 543 "    MOVEQ   R6, R1 \n"
 544 "    MOVEQ   R5, R3 \n"
 545 "    MOVEQ   R4, #1 \n"
 546 
 547 "loc_FF84D44C:\n"
 548 "    MOV     R0, #3 \n"
 549 "    BL      sub_FF86669C \n"
 550 "    CMP     R4, #0 \n"
 551 "    BNE     loc_FF84D484 \n"
 552 "    MOV     R6, #0 \n"
 553 "    MOV     R0, R8 \n"
 554 "    BL      sub_FF91AD24 \n"
 555 "    MOV     R5, R0 \n"
 556 "    B       loc_FF84D484 \n"
 557 
 558 "loc_FF84D470:\n"
 559 "    MOV     R5, #0x40 \n"
 560 "    B       loc_FF84D484 \n"
 561 
 562 "loc_FF84D478:\n"
 563 "    LDR     R1, =0x365 \n"
 564 "    LDR     R0, =0xFF84D320 /*'Mounter.c'*/ \n"
 565 "    BL      _DebugAssert \n"
 566 
 567 "loc_FF84D484:\n"
 568 "    STR     R6, [R7, #0x44]! \n"
 569 "    MOV     R0, #1 \n"
 570 "    STR     R5, [R7, #4] \n"
 571 "    LDMFD   SP!, {R4-R8,PC} \n"
 572 );
 573 }
 574 
 575 /*************************************************************/
 576 //** my_touchw_task @ 0xFF8E85F8 - 0xFF8E8630, length=15
 577 void __attribute__((naked,noinline)) my_touchw_task() {
 578 asm volatile (
 579 "    STMFD   SP!, {R4-R6,LR} \n"
 580 "    BL      sub_FF8E91FC \n"
 581 "    LDR     R5, =0xFFAA78B8 \n"
 582 "    LDR     R4, =0xD284 \n"
 583 
 584 "loc_FF8E8608:\n"
 585 "    LDR     R0, [R4, #0x1C] \n"
 586 "    MOV     R3, #0x1D0 \n"
 587 "    LDR     R2, =0xFF8E8818 /*'TouchWheel.c'*/ \n"
 588 "    MOV     R1, #0 \n"
 589 "    BL      sub_FF81BEB0 /*_TakeSemaphoreStrictly*/ \n"
 590 // loosely based on ixus860_sd870
 591 "     BL      kbd_is_blocked\n"
 592 "     MOV     R6, R0\n"
 593 "    LDR     R0, [R4, #0x24] \n"
 594 "    LDR     R1, [R4, #0x28] \n"
 595 
 596 // if not blocked, use original
 597 "     CMP     R6, #0\n"
 598 "     BEQ     bypass_skip_touch\n"
 599 
 600 // if kbd is blocked, skip touch events
 601 "     CMP     R0, #2\n"
 602 "     CMPEQ   R1, #1\n"
 603 "     BEQ     loc_FF8E8608\n"
 604 
 605 "bypass_skip_touch:\n"
 606 
 607 "    ADD     R0, R5, R0, LSL#4 \n"
 608 "    LDR     R0, [R0, R1, LSL#2] \n"
 609 "    BLX     R0 \n"
 610 "    B       loc_FF8E8608 \n"
 611 );
 612 }

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