root/platform/ixus950_sd850/sub/100c/capt_seq.c

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DEFINITIONS

This source file includes following definitions.
  1. sub_FFB0D8E4_my
  2. sub_FFB10B64_my
  3. sub_FFB0D80C_my
  4. capt_seq_task
  5. exp_drv_task
  6. sub_FF973980_my
  7. sub_FF93BD38_my

   1 #include "lolevel.h"
   2 #include "platform.h"
   3 #include "core.h"
   4 
   5 static long *nrflag = (long*)0xED44;
   6 
   7 #include "../../../generic/capt_seq.c"
   8 
   9 void __attribute__((naked,noinline)) sub_FFB0D8E4_my(long p)
  10 {
  11     asm volatile (
  12 "               STMFD   SP!, {R4,LR}\n"
  13 "               BL      sub_FFB0D420\n"
  14 "               LDR     R3, =0xAAB80\n"
  15 "               LDR     R2, [R3,#0x24]\n"
  16 "               CMP     R2, #0\n"
  17 "               MOV     R4, R0\n"
  18 "               MOV     R0, #0xC\n"
  19 "               BEQ     loc_FFB0D92C\n"
  20 "               BL      sub_FFB17EE8\n"
  21 "               TST     R0, #1\n"
  22 "               BEQ     loc_FFB0D92C\n"
  23 "               LDR     R3, [R4,#8]\n"
  24 "               LDR     R2, =0xED30\n"
  25 "               ORR     R3, R3, #0x40000000\n"
  26 "               MOV     R1, #1\n"
  27 "               STR     R1, [R2]\n"
  28 "               STR     R3, [R4,#8]\n"
  29 "               LDMFD   SP!, {R4,PC}\n"
  30 "loc_FFB0D92C:\n"
  31 "               BL      sub_FF826284\n"
  32 "               BL      sub_FF81BE94\n"
  33 "               STR     R0, [R4,#0x14]\n"
  34 "               MOV     R0, R4\n"
  35         "BL  sub_FFB10B64_my\n" //---> escape to My!
  36         "BL  capt_seq_hook_raw_here\n"  // + <----- RAW hook
  37 "               TST     R0, #1\n"
  38 "               LDRNE   R3, =0xED30\n"
  39 "               MOVNE   R2, #1\n"
  40 "               STRNE   R2, [R3]\n"
  41 "               LDMFD   SP!, {R4,PC}\n"
  42     );
  43 }
  44 
  45 void __attribute__((naked,noinline)) sub_FFB10B64_my(long p)
  46 {
  47     asm volatile (
  48 "               STMFD   SP!, {R4,LR}\n"
  49 "               MOV     R4, R0\n"
  50 "               SUB     SP, SP, #0xC\n"
  51 "               BL      sub_FFB115D4\n"
  52 
  53 //"             MOVL    R1, 0xFFFFFFFF\n"       // asm doesn't like this. Thus:
  54                "MVN     R1, #0\n"
  55 
  56 "               BL      sub_FFB21E2C\n" //ClearEventFlag
  57 "               MOV     R0, #0x8A\n"
  58 "               ADD     R1, SP, #4\n"
  59 "               MOV     R2, #4\n"
  60 "               BL      sub_FF81BC98\n"
  61 "               TST     R0, #1\n"
  62 "               BEQ     loc_FFB10BA4\n"
  63 
  64 "               MOV     R1, #0x1D0\n"
  65 // means: "     MOV     R1, #0x1D,28\n"
  66 
  67 "               LDR     R0, =0xFFB109E8\n" //"SsCaptureSeq.c"
  68 "               ADD     R1, R1, #2\n"
  69 "               BL      sub_FFB2F4F0\n" //DebugAssert
  70 "loc_FFB10BA4:\n"
  71 "               LDR     R3, =0xAAB80\n"
  72 "               LDR     R2, =0xAAC40\n"
  73 "               LDR     R0, [R3,#0x7C]\n"
  74 "               LDRSH   R1, [R2,#0xE]\n"
  75 "               BL      sub_FFA4226C\n"
  76 "               MOV     R0, R4\n"
  77 "               BL      sub_FFB1096C\n"
  78             "BL      wait_until_remote_button_is_released\n"
  79                "BL      capt_seq_hook_set_nr\n"  // + <- ADDED !!!!!
  80 "               LDR     R3, =0xED48\n"
  81 "               LDR     R0, [R3]\n"
  82                "B       sub_FFB10BC8\n"  // ---> jump to the original code in ROM, see below
  83 //FFB10BC8      BL      sub_FFA42780
  84     );
  85 }
  86 
  87 // orig. is sub_FFB0D80C
  88 void __attribute__((naked,noinline)) sub_FFB0D80C_my(long p)
  89 {
  90     asm volatile (
  91         
  92 "                STMFD   SP!, {R4,R5,LR}\n"
  93 "                LDR     R5, =0xAAB80\n"
  94 "                LDR     R4, [R0,#0xC]\n"
  95 "                LDR     R2, [R5,#0x24]\n"
  96 "                LDR     R3, [R4,#8]\n"
  97 "                CMP     R2, #0\n"
  98 "                ORR     R3, R3, #1\n"
  99 "                STR     R3, [R4,#8]\n"
 100 "                BNE     loc_FFB0D838\n"
 101 "                MOV     R0, #2\n"
 102 "                BL      sub_FFAF1CA4\n"
 103 "loc_FFB0D838:\n"
 104 "                BL      sub_FFB0E394\n" //Set_CMD25Write_62
 105 "                LDR     R3, [R5,#0x24]\n"
 106 "                CMP     R3, #0\n"
 107 "                BNE     loc_FFB0D8A4\n"
 108 "                MOV     R0, R4\n"
 109 "                BL      sub_FFB0F59C\n"
 110 "                TST     R0, #1\n"
 111 "                BEQ     loc_FFB0D868\n"
 112 "                MOV     R2, R4\n"
 113 "                MOV     R1, #1\n"
 114 "                LDMFD   SP!, {R4,R5,LR}\n"
 115 "                B       sub_FFB0BF7C\n"
 116 "loc_FFB0D868:\n"
 117 "                BL      sub_FF826284\n"
 118 "                BL      sub_FF81BE94\n"
 119 "                LDRH    R2, [R5]\n"
 120 //"                MOVL    R3, 0x420F\n"        // asm doesn't understand this. Thus:
 121                 "MOV    R3, #0x4200\n"
 122 // means:       "MOV    R3, #0x42,24\n"
 123                 "ADD    R3, R3, #0xF\n"
 124 
 125 "                CMP     R2, R3\n"
 126 "                STR     R0, [R4,#0x14]\n"
 127 "                BNE     loc_FFB0D88C\n"
 128 "                BL      sub_FFAF185C\n"
 129 "loc_FFB0D88C:\n"
 130 "                MOV     R0, R4\n"
 131 "                BL      sub_FFB10A4C\n"
 132 "                BL      sub_FFB11440\n"
 133 "                MOV     R0, R4\n"
 134 //"                BL      sub_FFB10B64\n"
 135                 "BL      sub_FFB10B64_my\n"  //---------> ESCAPE to My !!!!!
 136                 "BL      capt_seq_hook_raw_here\n"  // + <- ADDED !!!!!
 137 "                B       loc_FFB0D8B8\n"
 138 "loc_FFB0D8A4:\n"
 139 "                LDR     R3, =0xED30\n"
 140 "                LDR     R2, [R3]\n"
 141 "                CMP     R2, #0\n"
 142 "                MOVNE   R0, #0x1D\n"
 143 "                MOVEQ   R0, #0\n"
 144 "loc_FFB0D8B8:\n"
 145 "                MOV     R1, #1\n"
 146 "                MOV     R2, R4\n"
 147 "                BL      sub_FFB0BF7C\n"
 148 "                BL      sub_FFB10EE0\n"
 149 "                CMP     R0, #0\n"
 150 "                LDRNE   R3, [R4,#8]\n"
 151 "                ORRNE   R3, R3, #0x2000\n"
 152 "                STRNE   R3, [R4,#8]\n"
 153 "                LDMFD   SP!, {R4,R5,PC}\n"
 154     );
 155 }
 156 
 157 // orig. at FFB0DD10
 158 void __attribute__((naked,noinline)) capt_seq_task()
 159 {
 160         asm volatile (
 161 "                STMFD   SP!, {R4,LR}\n"
 162 "                SUB     SP, SP, #4\n"
 163 "                MOV     R4, SP\n"
 164 "                B       loc_FFB0DEB4\n"
 165 "loc_FFB0DD20:\n"
 166 "                LDR     R2, [SP]\n"
 167 "                LDR     R3, [R2]\n"
 168 "                MOV     R0, R2\n"
 169 "                CMP     R3, #0x17\n"
 170 "                LDRLS   PC, [PC,R3,LSL#2]\n"
 171 "                B       loc_FFB0DE88\n"
 172 "                .long loc_FFB0DD98\n"
 173 "                .long loc_FFB0DDB8\n"
 174 "                .long loc_FFB0DDCC\n"
 175 "                .long loc_FFB0DDE0\n"
 176 "                .long loc_FFB0DDD8\n"
 177 "                .long loc_FFB0DDE8\n"
 178 "                .long loc_FFB0DDF0\n"
 179 "                .long loc_FFB0DDFC\n"
 180 "                .long loc_FFB0DE04\n"
 181 "                .long loc_FFB0DE10\n"
 182 "                .long loc_FFB0DE18\n"
 183 "                .long loc_FFB0DE20\n"
 184 "                .long loc_FFB0DE28\n"
 185 "                .long loc_FFB0DE30\n"
 186 "                .long loc_FFB0DE38\n"
 187 "                .long loc_FFB0DE40\n"
 188 "                .long loc_FFB0DE48\n"
 189 "                .long loc_FFB0DE54\n"
 190 "                .long loc_FFB0DE5C\n"
 191 "                .long loc_FFB0DE64\n"
 192 "                .long loc_FFB0DE6C\n"
 193 "                .long loc_FFB0DE78\n"
 194 "                .long loc_FFB0DE80\n"
 195 "                .long loc_FFB0DE9C\n"
 196 "loc_FFB0DD98:\n"
 197 "                BL      sub_FFB0E3BC\n"
 198 // only do quick press hack if overrides are active
 199 "                BL      captseq_hack_override_active\n" // returns 1 if tv or sv override in effect
 200 "                STR     R0,[SP,#-4]!\n" // push return value
 201                 "BL      shooting_expo_param_override\n"   // + <- ADDED !!!!!
 202 "                BL      sub_FFB0BA04\n"
 203 "                LDR     R3, =0xAAB80\n"
 204 "                LDR     R0,[SP],#4\n" // pop override hack
 205 "                CMP     R0, #1\n"     // +
 206 "                MOVEQ   R0, #0\n"     // +
 207 "                STREQ   R0, [R3,#0x24]\n"  // fixes overrides behavior at short shutter press
 208 "                LDRNE   R0, [R3,#0x24]\n" // modified NE
 209 "                CMPNE   R0, #0\n"         // modified NE
 210 "                BEQ     loc_FFB0DE98\n"
 211 "                BL      sub_FFB0D8E4_my\n"   //<---- extra RAW hook inside
 212 "                B       loc_FFB0DE98\n"
 213 "loc_FFB0DDB8:\n"
 214 //"                BL      sub_FFB0D80C\n"
 215 "                BL      sub_FFB0D80C_my\n"  //---------> ESCAPE to My !!!!!
 216 "loc_FFB0DDBC:\n"
 217 "                LDR     R2, =0xAAB80\n"
 218 "                MOV     R3, #0\n"
 219 "                STR     R3, [R2,#0x24]\n"
 220 "                B       loc_FFB0DE98\n"
 221 "loc_FFB0DDCC:\n"
 222 "                MOV     R0, #1\n"
 223 "                BL      sub_FFB0E5E8\n"
 224 "                B       loc_FFB0DE98\n"
 225 "loc_FFB0DDD8:\n"
 226 "                BL      sub_FFB0DFA0\n"
 227 "                B       loc_FFB0DDBC\n"
 228 "loc_FFB0DDE0:\n"
 229 "                BL      sub_FFB0E374\n" //BackLightDrv_LcdBackLightOff_16
 230 "                B       loc_FFB0DDBC\n"
 231 "loc_FFB0DDE8:\n"
 232 "                BL      sub_FFB0E384\n"
 233 "                B       loc_FFB0DE98\n"
 234 "loc_FFB0DDF0:\n"
 235 "                BL      sub_FFB0E4D8\n"
 236 "                BL      sub_FFB0BA04\n"
 237 "                B       loc_FFB0DE98\n"
 238 "loc_FFB0DDFC:\n"
 239 "                BL      sub_FFB0D9BC\n"
 240 "                B       loc_FFB0DE98\n"
 241 "loc_FFB0DE04:\n"
 242 "                BL      sub_FFB0E54C\n"
 243 "                BL      sub_FFB0BA04\n"
 244 "                B       loc_FFB0DE98\n"
 245 "loc_FFB0DE10:\n"
 246 "                BL      sub_FFB0E374\n" //BackLightDrv_LcdBackLightOff_16
 247 "                B       loc_FFB0DE98\n"
 248 "loc_FFB0DE18:\n"
 249 "                BL      sub_FFB0FCD0\n"
 250 "                B       loc_FFB0DE98\n"
 251 "loc_FFB0DE20:\n"
 252 "                BL      sub_FFB0FEA4\n"
 253 "                B       loc_FFB0DE98\n"
 254 "loc_FFB0DE28:\n"
 255 "                BL      sub_FFB0FF38\n"
 256 "                B       loc_FFB0DE98\n"
 257 "loc_FFB0DE30:\n"
 258 "                BL      sub_FFB10034\n"
 259 "                B       loc_FFB0DE98\n"
 260 "loc_FFB0DE38:\n"
 261 "                BL      sub_FFB102BC\n"
 262 "                B       loc_FFB0DE98\n"
 263 "loc_FFB0DE40:\n"
 264 "                BL      sub_FFB1030C\n"
 265 "                B       loc_FFB0DE98\n"
 266 "loc_FFB0DE48:\n"
 267 "                MOV     R0, #0\n"
 268 "                BL      sub_FFB10360\n"
 269 "                B       loc_FFB0DE98\n"
 270 "loc_FFB0DE54:\n"
 271 "                BL      sub_FFB10534\n"
 272 "                B       loc_FFB0DE98\n"
 273 "loc_FFB0DE5C:\n"
 274 "                BL      sub_FFB105D0\n"
 275 "                B       loc_FFB0DE98\n"
 276 "loc_FFB0DE64:\n"
 277 "                BL      sub_FFB1069C\n"
 278 "                B       loc_FFB0DE98\n"
 279 "loc_FFB0DE6C:\n"
 280 "                BL      sub_FFB0E73C\n"
 281 "                BL      sub_FFB0D730\n"
 282 "                B       loc_FFB0DE98\n"
 283 "loc_FFB0DE78:\n"
 284 "                BL      sub_FFB10174\n"
 285 "                B       loc_FFB0DE98\n"
 286 "loc_FFB0DE80:\n"
 287 "                BL      sub_FFB101D0\n"
 288 "                B       loc_FFB0DE98\n"
 289 "loc_FFB0DE88:\n"
 290 "                MOV     R1, #0x4F0\n"
 291 "                LDR     R0, =0xFFB0D58C\n" //=aSsshoottask_c
 292 "                ADD     R1, R1, #1\n"
 293 "                BL      sub_FFB2F4F0\n" //DebugAssert
 294 "loc_FFB0DE98:\n"
 295 "                LDR     R2, [SP]\n"
 296 "loc_FFB0DE9C:\n"
 297 "                LDR     R3, =0x84428\n"
 298 "                LDR     R1, [R2,#4]\n"
 299 "                LDR     R0, [R3]\n"
 300 "                BL      sub_FFB21C90\n" //SetEventFlag
 301 "                LDR     R0, [SP]\n"
 302 "                BL      sub_FFB0D60C\n"
 303 "loc_FFB0DEB4:\n"
 304 "                LDR     R3, =0x8442C\n"
 305 "                MOV     R1, R4\n"
 306 "                LDR     R0, [R3]\n"
 307 "                MOV     R2, #0\n"
 308 "                BL      sub_FFB223A8\n" //ReceiveMessageQueue
 309 "                TST     R0, #1\n"
 310 "                BEQ     loc_FFB0DD20\n"
 311 "                MOV     R1, #0x410\n"
 312 "                LDR     R0, =0xFFB0D58C\n" //=aSsshoottask_c
 313 "                ADD     R1, R1, #5\n"
 314 "                BL      sub_FFB2F4F0\n" //DebugAssert
 315 "                BL      sub_FFB2396C\n"
 316 "                ADD     SP, SP, #4\n"
 317 "                LDMFD   SP!, {R4,PC}\n"
 318         );
 319 }
 320 
 321 
 322 
 323 
 324 
 325 
 326 
 327 /*
 328 ROM:FF976A78     var_38          = -0x38
 329 ROM:FF976A78     var_34          = -0x34
 330 ROM:FF976A78     var_30          = -0x30
 331 ROM:FF976A78     var_24          = -0x24
 332 ROM:FF976A78     var_20          = -0x20
 333 ROM:FF976A78     var_1E          = -0x1E
 334 ROM:FF976A78     var_1C          = -0x1C
 335 */
 336 //void __attribute__((naked,noinline)) _task_ExpDrvTask() {
 337 void __attribute__((naked,noinline)) exp_drv_task() {
 338  asm volatile(
 339                  "STMFD   SP!, {R4-R8,LR}\n" // @ Store Block to Memory
 340                  "SUB     SP, SP, #0x20\n" //   @ Rd = Op1 - Op2
 341                  "ADD     R7, SP, #0x4\n" //  @ Rd = Op1 + Op2
 342                  "B       loc_FF976F88\n" //    @ Branch
 343 
 344 
 345      "loc_FF976A88:\n" //                           @ CODE XREF: task_ExpDrvTask+530
 346                  "CMP     R2, #0x22\n" // @ '"' @ Set cond. codes on Op1 - Op2
 347                  "BNE     loc_FF976AA0\n"    //@ Branch
 348 
 349                  "LDR     R0, [R12,#0x8C]\n" //@ Load from Memory
 350                  "MOV     LR, PC\n"          //@ Rd = Op2
 351                  "LDR     PC, [R12,#0x88]\n" //@ Indirect Jump
 352                  "B       loc_FF976B04\n"    //@ Branch
 353 
 354 
 355 
 356      "loc_FF976AA0:\n"                           //@ CODE XREF: task_ExpDrvTask+14
 357                  "CMP     R2, #0x1D\n"       //@ Set cond. codes on Op1 - Op2
 358                  "BNE     loc_FF976AB4\n"    //@ Branch
 359 
 360                  "MOV     R0, R12\n"         //@ Rd = Op2
 361                  "BL      sub_FF976948\n"    //@ Branch with Link
 362 
 363                  "B       loc_FF976AF4\n"    //@ Branch
 364 
 365 
 366 
 367      "loc_FF976AB4:\n"                           //@ CODE XREF: task_ExpDrvTask+2C
 368                  "CMP     R2, #0x1E\n"       //@ Set cond. codes on Op1 - Op2
 369                  "BNE     loc_FF976AC8\n"    //@ Branch
 370 
 371                  "MOV     R0, R12\n"         //@ Rd = Op2
 372                  "BL      sub_FF9769A4\n"    //@ Branch with Link
 373 
 374                  "B       loc_FF976AF4\n"    //@ Branch
 375 
 376 
 377 
 378      "loc_FF976AC8:\n"                           //@ CODE XREF: task_ExpDrvTask+40
 379                  "SUB     R3, R2, #0x1F\n"   //@ Rd = Op1 - Op2
 380                  "CMP     R3, #1\n"          //@ Set cond. codes on Op1 - Op2
 381                  "BHI     loc_FF976AE0\n"    //@ Branch
 382 
 383                  "MOV     R0, R12\n"         //@ Rd = Op2
 384                  "BL      sub_FF976A00\n"    //@ Branch with Link
 385 
 386                  "B       loc_FF976AF4\n"    //@ Branch
 387 
 388 
 389 
 390      "loc_FF976AE0:\n"                           //@ CODE XREF: task_ExpDrvTask+58
 391                  "CMP     R2, #0x21\n"           // @ '!' Set cond. codes on Op1 - Op2
 392                  "BNE     loc_FF976B10\n"    //@ Branch
 393 
 394                  "BL      sub_FF93C0BC\n"    //@ Branch with Link
 395 
 396                  "BL      sub_FF93F1F4\n"    //@ Branch with Link
 397 
 398                  "BL      sub_FF93E42C\n"    //@ Branch with Link
 399 
 400 
 401      "loc_FF976AF4:\n"                           //@ CODE XREF: task_ExpDrvTask+38
 402                  "LDR     R3, [SP,#4]\n"     //@ Load from Memory
 403                  "LDR     R0, [R3,#0x8C]\n"  //@ Load from Memory
 404                  "MOV     LR, PC\n"          //@ Rd = Op2
 405                  "LDR     PC, [R3,#0x88]\n"  //@ Indirect Jump
 406 
 407      "loc_FF976B04:\n"                           //@ CODE XREF: task_ExpDrvTask+24
 408                  "LDR     R0, [SP,#0x4]\n" //@ Load from Memory
 409                  "BL      sub_FF9722A8\n"    //@ Branch with Link
 410 
 411                  "B       loc_FF976F88\n"    //@ Branch
 412 
 413 
 414      "loc_FF976B10:\n"                           //@ CODE XREF: task_ExpDrvTask+6C
 415                  "CMP     R2, #0xD\n"        //@ Set cond. codes on Op1 - Op2
 416                  "MOV     R8, #1\n"          //@ Rd = Op2
 417                  "BNE     loc_FF976B80\n"    //@ Branch
 418 
 419                  "LDR     R1, [R12,#0x7C]\n" //@ Load from Memory
 420                  "ADD     R1, R1, R1,LSL#1\n" //@ Rd = Op1 + Op2
 421                  "ADD     R1, R12, R1,LSL#2\n" //@ Rd = Op1 + Op2
 422                  "ADD     R6, SP, #0x14\n"   //@ Rd = Op1 + Op2
 423                  "SUB     R1, R1, #8\n"      //@ Rd = Op1 - Op2
 424                  "MOV     R2, #0xC\n"        //@ Rd = Op2
 425                  "MOV     R0, R6\n"          //@ Rd = Op2
 426                  "BL      _memcpy\n"          //@ Branch with Link
 427 
 428                  "LDR     R0, [SP,#4]\n" //@ Load from Memory
 429                  "BL      sub_FF974F0C\n"    //@ Branch with Link
 430 
 431                  "LDR     R3, [SP,#04]\n" //@ Load from Memory
 432                  "LDR     R1, [R3,#0x7C]\n"  //@ Load from Memory
 433                  "LDR     R2, [R3,#0x8C]\n"  //@ Load from Memory
 434                  "ADD     R0, R3, #4\n"      //@ Rd = Op1 + Op2
 435                  "MOV     LR, PC\n"          //@ Rd = Op2
 436                  "LDR     PC, [R3,#0x88]\n"  //@ Indirect Jump
 437                  "LDR     R0, [SP,#4]\n" //@ Load from Memory
 438                  "BL      sub_FF9751D8\n"    //@ Branch with Link
 439 
 440                  "LDR     R3, [SP,#04]\n" //@ Load from Memory
 441                  "ADD     R0, R3, #4\n"      //@ Rd = Op1 + Op2
 442                  "LDR     R1, [R3,#0x7C]\n"  //@ Load from Memory
 443                  "LDR     R2, [R3,#0x94]\n"  //@ Load from Memory
 444                  "MOV     LR, PC\n"          //@ Rd = Op2
 445                  "LDR     PC, [R3,#0x90]\n"  //@ Indirect Jump
 446                  "B       loc_FF976ED0\n"    //@ Branch
 447 
 448 
 449 
 450      "loc_FF976B80:\n"                           //@ CODE XREF: task_ExpDrvTask+A0
 451                  "SUB     R3, R2, #0xE\n"    //@ Rd = Op1 - Op2
 452                  "CMP     R3, #1\n"          //@ Set cond. codes on Op1 - Op2
 453                  "BHI     loc_FF976C3C\n"    //@ Branch
 454 
 455                  "ADD     R6, SP, #0x14\n" //@ Rd = Op1 + Op2
 456                  "ADD     R5, SP, #0x8\n" //@ Rd = Op1 + Op2
 457                  "MOV     R0, R12\n"         //@ Rd = Op2
 458                  "MOV     R1, R6\n"          //@ Rd = Op2
 459                  "MOV     R2, R5\n"          //@ Rd = Op2
 460                  "BL      sub_FF9752C8\n"    //@ Branch with Link
 461 
 462                  "MOV     R4, R0\n"          //@ Rd = Op2
 463                  "CMP     R4, #5\n"          //@ Set cond. codes on Op1 - Op2
 464                  "CMPNE   R4, #1\n"          //@ Set cond. codes on Op1 - Op2
 465                  "BNE     loc_FF976BD4\n"    //@ Branch
 466 
 467                  "LDR     R12, [SP,#0x4]\n" //@ Load from Memory
 468                  "MOV     R0, R5\n"          //@ Rd = Op2
 469                  "LDR     R1, [R12,#0x7C]\n" //@ Load from Memory
 470                  "MOV     R2, R4\n"          //@ Rd = Op2
 471                  "LDR     R3, [R12,#0x8C]\n" //@ Load from Memory
 472                  "MOV     LR, PC\n"          //@ Rd = Op2
 473                  "LDR     PC, [R12,#0x88]\n" //@ Indirect Jump
 474                  "B       loc_FF976C0C\n"    //@ Branch
 475 
 476 
 477 
 478      "loc_FF976BD4:\n"                           //@ CODE XREF: task_ExpDrvTask+138
 479                  "CMP     R4, #6\n"          //@ Set cond. codes on Op1 - Op2
 480                  "CMPNE   R4, #2\n"          //@ Set cond. codes on Op1 - Op2
 481                  "BNE     loc_FF976C1C\n"    //@ Branch
 482 
 483                  "LDR     R12, [SP,#0x4]\n" //@ Load from Memory
 484                  "MOV     R0, R5\n"          //@ Rd = Op2
 485                  "MOV     R1, R8\n"          //@ Rd = Op2
 486                  "MOV     R2, R4\n"          //@ Rd = Op2
 487                  "LDR     R3, [R12,#0x8C]\n" //@ Load from Memory
 488                  "MOV     LR, PC\n"          //@ Rd = Op2
 489                  "LDR     PC, [R12,#0x88]\n" //@ Indirect Jump
 490                  "MOV     R1, R6\n"          //@ Rd = Op2
 491                  "LDR     R0, [SP,#0x4]\n" //@ Load from Memory
 492                  "MOV     R2, R5\n"          //@ Rd = Op2
 493                  "BL      sub_FF976578\n"    //@ Branch with Link
 494 
 495 
 496      "loc_FF976C0C:\n"                           //@ CODE XREF: task_ExpDrvTask+158
 497                  "MOV     R1, R4\n"          //@ Rd = Op2
 498                  "LDR     R0, [SP,#04]\n" //@ Load from Memory
 499                  "BL      sub_FF9768DC\n"    //@ Branch with Link
 500 
 501                  "B       loc_FF976ED0\n"    //@ Branch
 502 
 503 
 504      "loc_FF976C1C:\n"                           //@ CODE XREF: task_ExpDrvTask+164
 505                  "LDR     R12, [SP,#0x4]\n" //@ Load from Memory
 506                  "MOV     R2, R4\n"          //@ Rd = Op2
 507                  "ADD     R0, R12, #4\n"     //@ Rd = Op1 + Op2
 508                  "LDR     R1, [R12,#0x7C]\n" //@ Load from Memory
 509                  "LDR     R3, [R12,#0x8C]\n" //@ Load from Memory
 510                  "MOV     LR, PC\n"          //@ Rd = Op2
 511                  "LDR     PC, [R12,#0x88]\n" //@ Indirect Jump
 512                  "B       loc_FF976ED0\n"    //@ Branch
 513 
 514 
 515 
 516      "loc_FF976C3C:\n"                           //@ CODE XREF: task_ExpDrvTask+110
 517                  "SUB     R3, R2, #0x19\n"   //@ Rd = Op1 - Op2
 518                  "CMP     R3, #1\n"          //@ Set cond. codes on Op1 - Op2
 519                  "BHI     loc_FF976C94\n"    //@ Branch
 520 
 521                  "LDR     R1, [R12,#0x7C]\n" //@ Load from Memory
 522                  "ADD     R1, R1, R1,LSL#1\n" //@ Rd = Op1 + Op2
 523                  "ADD     R1, R12, R1,LSL#2\n" //@ Rd = Op1 + Op2
 524                  "ADD     R6, SP, #0x14\n" //@ Rd = Op1 + Op2
 525                  "SUB     R1, R1, #8\n"      //@ Rd = Op1 - Op2
 526                  "MOV     R2, #0xC\n"        //@ Rd = Op2
 527                  "MOV     R0, R6\n"          //@ Rd = Op2
 528                  "BL      _memcpy\n"          //@ Branch with Link
 529 
 530                  "LDR     R0, [SP,#0x4]\n" //@ Load from Memory
 531                  "BL      sub_FF97430C\n"    //@ Branch with Link
 532 
 533                  "LDR     R3, [SP,#0x4]\n" //@ Load from Memory
 534                  "ADD     R0, R3, #4\n"      //@ Rd = Op1 + Op2
 535                  "LDR     R1, [R3,#0x7C]\n"  //@ Load from Memory
 536                  "LDR     R2, [R3,#0x8C]\n"  //@ Load from Memory
 537                  "MOV     LR, PC\n"          //@ Rd = Op2
 538                  "LDR     PC, [R3,#0x88]\n"  //@ Indirect Jump
 539                  "LDR     R0, [SP,#0x4]\n" //@ Load from Memory
 540                  "BL      sub_FF97462C\n"    //@ Branch with Link
 541 
 542                  "B       loc_FF976ED0\n"    //@ Branch
 543 
 544 
 545 
 546      "loc_FF976C94:\n"                           //@ CODE XREF: task_ExpDrvTask+1CC
 547                  "ADD     R6, SP, #0x14\n" //@ Rd = Op1 + Op2
 548                  "ADD     R1, R12, #4\n"     //@ Rd = Op1 + Op2
 549                  "MOV     R2, #0xC\n"        //@ Rd = Op2
 550                  "MOV     R0, R6\n"          //@ Rd = Op2
 551                  "BL      _memcpy\n"          //@ Branch with Link
 552 
 553                  "LDR     R12, [SP,#0x4]\n" //@ Load from Memory
 554                  "LDR     R3, [R12]\n"       //@ Load from Memory
 555                  "MOV     R2, R12\n"         //@ Rd = Op2
 556                  "CMP     R3, #0x1C\n"       //@ Set cond. codes on Op1 - Op2
 557                  "LDRLS   PC, [PC,R3,LSL#2]\n" //@ Indirect Jump
 558 
 559                  "B       loc_FF976EBC\n"    //@ Branch
 560 
 561 
 562                  ".long loc_FF976D34\n"
 563                  ".long loc_FF976D40\n"
 564                  ".long loc_FF976D4C\n"
 565                  ".long loc_FF976D4C\n"
 566                  ".long loc_FF976D34\n"
 567                  ".long loc_FF976D40\n"
 568                  ".long loc_FF976D4C\n"
 569                  ".long loc_FF976D4C\n"
 570                  ".long loc_FF976D70\n"
 571                  ".long loc_FF976D70\n"
 572                  ".long loc_FF976E90\n"
 573                  ".long loc_FF976E9C\n"
 574                  ".long loc_FF976EAC\n"
 575                  ".long loc_FF976EBC\n"
 576                  ".long loc_FF976EBC\n"
 577                  ".long loc_FF976EBC\n"
 578                  ".long loc_FF976D58\n"
 579                  ".long loc_FF976D64\n"
 580                  ".long loc_FF976D80\n"
 581                  ".long loc_FF976D8C\n"
 582                  ".long loc_FF976DC4\n"
 583                  ".long loc_FF976DFC\n"
 584                  ".long loc_FF976E34\n"
 585                  ".long loc_FF976E6C\n"
 586                  ".long loc_FF976E6C\n"
 587                  ".long loc_FF976EBC\n"
 588                  ".long loc_FF976EBC\n"
 589                  ".long loc_FF976E78\n"
 590                  ".long loc_FF976E84\n"
 591 
 592 
 593      "loc_FF976D34:\n"                           //@ CODE XREF: task_ExpDrvTask+240
 594                  "MOV     R0, R2\n"          //@ Rd = Op2
 595                  "BL      sub_FF972C08\n"    //@ Branch with Link
 596 
 597                  "B       loc_FF976EB8\n"    //@ Branch
 598 
 599      "loc_FF976D40:\n"                           //@ CODE XREF: task_ExpDrvTask+240
 600                  "MOV     R0, R2\n"          //@ Rd = Op2
 601                  "BL      sub_FF972EAC\n"    //@ Branch with Link
 602 
 603                  "B       loc_FF976EB8\n"    //@ Branch
 604 
 605      "loc_FF976D4C:\n"                           //@ CODE XREF: task_ExpDrvTask+240
 606                  "MOV     R0, R2\n"          //@ Rd = Op2
 607                  "BL      sub_FF973120\n"    //@ Branch with Link
 608 
 609                  "B       loc_FF976EB8\n"    //@ Branch
 610 
 611      "loc_FF976D58:\n"                           //@ CODE XREF: task_ExpDrvTask+240
 612                  "MOV     R0, R2\n"          //@ Rd = Op2
 613                  "BL      sub_FF97341C\n"    //@ Branch with Link
 614 
 615                  "B       loc_FF976EB8\n"    //@ Branch
 616 
 617      "loc_FF976D64:\n"                           //@ CODE XREF: task_ExpDrvTask+240
 618                  "MOV     R0, R2\n"          //@ Rd = Op2
 619                  "BL      sub_FF973684\n"    //@ Branch with Link
 620 
 621                  "B       loc_FF976EB8\n"    //@ Branch
 622 
 623      "loc_FF976D70:\n"                           //@ CODE XREF: task_ExpDrvTask+240
 624                  "MOV     R0, R2\n"          //@ Rd = Op2
 625 //                 "BL      sub_FF973980\n"    //@ Branch with Link
 626                  "BL      sub_FF973980_my\n"    //@ Branch with Link this is the place where the function lies where ewvar also creates its own version of, so we just do the same here
 627 
 628                  "MOV     R8, #0\n"          //@ Rd = Op2
 629                  "B       loc_FF976EB8\n"    //@ Branch
 630 
 631      "loc_FF976D80:\n"                           //@ CODE XREF: task_ExpDrvTask+240
 632                  "MOV     R0, R2\n"          //@ Rd = Op2
 633                  "BL      sub_FF973AE0\n"    //@ Branch with Link
 634 
 635                  "B       loc_FF976EB8\n"    //@ Branch
 636 
 637 
 638      "loc_FF976D8C:\n"                           //@ CODE XREF: task_ExpDrvTask+240
 639                  "LDRH    R1, [R2,#4]\n"     //@ Load from Memory
 640 //                 "LDR     R3, =0x2E4A8\n"  //@ Load from Memory
 641                  "LDR     R3, =0x2E4A8\n"  //@ Load from Memory
 642                  "STRH    R1, [SP,#0x14]\n" //@ Store to Memory
 643                  "LDRH    R1, [R3,#6]\n"     //@ Load from Memory
 644                  "STRH    R1, [SP,#0x1A]\n" //@ Store to Memory
 645                  "LDRH    R1, [R3,#2]\n"     //@ Load from Memory
 646                  "STRH    R1, [SP,#0x16]\n" //@ Store to Memory
 647                  "LDRH    R3, [R3,#4]\n"     //@ Load from Memory
 648                  "STRH    R3, [SP,#0x18]\n" //@ Store to Memory
 649                  "MOV     R0, R2\n"          //@ Rd = Op2
 650                  "LDRH    R2, [R2,#0xC]\n"   //@ Load from Memory
 651                  "STRH    R2, [SP,#0x1C]\n" //@ Store to Memory
 652                  "BL      sub_FF973DDC\n"    //@ Branch with Link
 653 
 654                  "B       loc_FF976EB8\n"    //@ Branch
 655 
 656 
 657      "loc_FF976DC4:\n"                           //@ CODE XREF: task_ExpDrvTask+240
 658                  "MOV     R0, R2\n"          //@ Rd = Op2
 659                  "LDRH    R2, [R2,#4]\n"     //@ Load from Memory
 660                  "LDR     R3, =0x2E4A8\n"  //@ Load from Memory
 661                  "STRH    R2, [SP,#0x14]\n" //@ Store to Memory
 662                  "LDRH    R2, [R3,#8]\n"     //@ Load from Memory
 663                  "STRH    R2, [SP,#0x1C]\n" //@ Store to Memory
 664                  "LDRH    R1, [R3,#2]\n"     //@ Load from Memory
 665                  "STRH    R1, [SP,#0x16]\n" //@ Store to Memory
 666                  "LDRH    R2, [R3,#4]\n"     //@ Load from Memory
 667                  "STRH    R2, [SP,#0x18]\n" //@ Store to Memory
 668                  "LDRH    R3, [R3,#6]\n"     //@ Load from Memory
 669                  "STRH    R3, [SP,#0x1A]\n" //@ Store to Memory
 670                  "BL      sub_FF973F04\n"    //@ Branch with Link
 671 
 672                  "B       loc_FF976EB8\n"    //@ Branch
 673 
 674 
 675      "loc_FF976DFC:\n"                           //@ CODE XREF: task_ExpDrvTask+240
 676                  "LDR     R3, =0x2E4A8\n"  //@ Load from Memory
 677                  "LDRH    R1, [R3]\n"        //@ Load from Memory
 678                  "STRH    R1, [SP,#0x14]\n" //@ Store to Memory
 679                  "MOV     R0, R2\n"          //@ Rd = Op2
 680                  "LDRH    R2, [R2,#6]\n"     //@ Load from Memory
 681                  "STRH    R2, [SP,#0x16]\n" //@ Store to Memory
 682                  "LDRH    R2, [R3,#8]\n"     //@ Load from Memory
 683                  "STRH    R2, [SP,#0x1C]\n" //@ Store to Memory
 684                  "LDRH    R1, [R3,#4]\n"     //@ Load from Memory
 685                  "STRH    R1, [SP,#0x18]\n" //@ Store to Memory
 686                  "LDRH    R3, [R3,#6]\n"     //@ Load from Memory
 687                  "STRH    R3, [SP,#0x1A]\n" //@ Store to Memory
 688                  "BL      sub_FF973FC8\n"    //@ Branch with Link
 689 
 690                  "B       loc_FF976EB8\n"    //@ Branch
 691 
 692 
 693      "loc_FF976E34:\n"                           //@ CODE XREF: task_ExpDrvTask+240
 694                  "LDR     R3, =0x2E4A8\n"  //@ Load from Memory
 695                  "LDRH    R1, [R3,#6]\n"     //@ Load from Memory
 696                  "STRH    R1, [SP,#0x1A]\n" //@ Store to Memory
 697                  "LDRH    R1, [R3]\n"        //@ Load from Memory
 698                  "STRH    R1, [SP,#0x14]\n" //@ Store to Memory
 699                  "LDRH    R1, [R3,#2]\n"     //@ Load from Memory
 700                  "STRH    R1, [SP,#0x16]\n" //@ Store to Memory
 701                  "LDRH    R3, [R3,#4]\n"     //@ Load from Memory
 702                  "STRH    R3, [SP,#0x18]\n" //@ Store to Memory
 703                  "MOV     R0, R2\n"          //@ Rd = Op2
 704                  "LDRH    R2, [R2,#0xC]\n"   //@ Load from Memory
 705                  "STRH    R2, [SP,#0x1C]\n" //@ Store to Memory
 706                  "BL      sub_FF974080\n"    //@ Branch with Link
 707 
 708                  "B       loc_FF976EB8\n"    //@ Branch
 709 
 710      "loc_FF976E6C:\n"                           //@ CODE XREF: task_ExpDrvTask+240
 711                  "MOV     R0, R2\n"          //@ Rd = Op2
 712                  "BL      sub_FF974130\n"    //@ Branch with Link
 713 
 714                  "B       loc_FF976EB8\n"    //@ Branch
 715 
 716      "loc_FF976E78:\n"                           //@ CODE XREF: task_ExpDrvTask+240
 717                  "MOV     R0, R2\n"          //@ Rd = Op2
 718                  "BL      sub_FF974778\n"    //@ Branch with Link
 719 
 720                  "B       loc_FF976EB8\n"    //@ Branch
 721 
 722      "loc_FF976E84:\n"                           //@ CODE XREF: task_ExpDrvTask+240
 723                  "MOV     R0, R2\n"          //@ Rd = Op2
 724                  "BL      sub_FF974A24\n"    //@ Branch with Link
 725 
 726                  "B       loc_FF976EB8\n"    //@ Branch
 727 
 728      "loc_FF976E90:\n"                           //@ CODE XREF: task_ExpDrvTask+240
 729                  "MOV     R0, R2\n"          //@ Rd = Op2
 730                  "BL      sub_FF974BE0\n"    //@ Branch with Link
 731 
 732                  "B       loc_FF976EB8\n"    //@ Branch
 733 
 734      "loc_FF976E9C:\n"                           //@ CODE XREF: task_ExpDrvTask+240
 735                  "MOV     R0, R2\n"          //@ Rd = Op2
 736                  "MOV     R1, #0\n"          //@ Rd = Op2
 737                  "BL      sub_FF974DC8\n"    //@ Branch with Link
 738 
 739                  "B       loc_FF976EB8\n"    //@ Branch
 740 
 741      "loc_FF976EAC:\n"                           //@ CODE XREF: task_ExpDrvTask+240
 742                  "MOV     R0, R2\n"          //@ Rd = Op2
 743                  "MOV     R1, #1\n"          //@ Rd = Op2
 744                  "BL      sub_FF974DC8\n"    //@ Branch with Link
 745 
 746 
 747      "loc_FF976EB8:\n"                           //@ CODE XREF: task_ExpDrvTask+2C4
 748                  "LDR     R12, [SP,#0x4]\n" //@ Load from Memory
 749 
 750      "loc_FF976EBC:\n"                           //@ CODE XREF: task_ExpDrvTask+240
 751                  "ADD     R0, R12, #4\n"     //@ Rd = Op1 + Op2
 752                  "LDR     R1, [R12,#0x7C]\n" //@ Load from Memory
 753                  "LDR     R2, [R12,#0x8C]\n" //@ Load from Memory
 754                  "MOV     LR, PC\n"          //@ Rd = Op2
 755                  "LDR     PC, [R12,#0x88]\n" //@ Indirect Jump
 756 
 757      "loc_FF976ED0:\n"                           //@ CODE XREF: task_ExpDrvTask+104
 758                  "CMP     R8, #1\n"          //@ Set cond. codes on Op1 - Op2
 759                  "BNE     loc_FF976EF8\n"    //@ Branch
 760 
 761                  "LDR     R1, [SP,#0x4]\n" //@ Load from Memory
 762                  "LDR     R3, [R1,#0x7C]\n"  //@ Load from Memory
 763                  "ADD     R3, R3, R3,LSL#1\n" //@ Rd = Op1 + Op2
 764                  "ADD     R1, R1, R3,LSL#2\n" //@ Rd = Op1 + Op2
 765                  "MOV     R0, R6\n"          //@ Rd = Op2
 766                  "SUB     R1, R1, #8\n"      //@ Rd = Op1 - Op2
 767                  "BL      sub_FF9728C0\n"    //@ Branch with Link
 768 
 769                  "B       loc_FF976F74\n"    //@ Branch
 770 
 771 
 772      "loc_FF976EF8:\n"                           //@ CODE XREF: task_ExpDrvTask+45C
 773                  "LDR     R3, [SP,#0x4]\n" //@ Load from Memory
 774                  "LDR     R2, [R3]\n"        //@ Load from Memory
 775                  "CMP     R2, #9\n"          //@ Set cond. codes on Op1 - Op2
 776                  "BNE     loc_FF976F40\n"    //@ Branch
 777 
 778                  "MOV     R4, #0\n"          //@ Rd = Op2
 779                  "MOV     R1, #1\n"          //@ Rd = Op2
 780                  "MOV     R2, R1\n"          //@ Rd = Op2
 781                  "MOV     R3, R1\n"          //@ Rd = Op2
 782                  "MOV     R0, R4\n"          //@ Rd = Op2
 783                  "STR     R4, [SP]\n" //@ Store to Memory
 784                  "BL      sub_FF972804\n"    //@ Branch with Link
 785 
 786                  "MOV     R1, #1\n"          //@ Rd = Op2
 787                  "MOV     R0, R4\n"          //@ Rd = Op2
 788                  "MOV     R2, R1\n"          //@ Rd = Op2
 789                  "MOV     R3, R1\n"          //@ Rd = Op2
 790                  "STR     R4, [SP]\n" //@ Store to Memory
 791                  "BL      sub_FF972A5C\n"    //@ Branch with Link
 792 
 793                  "B       loc_FF976F74\n"    //@ Branch
 794 
 795 
 796      "loc_FF976F40:\n"                           //@ CODE XREF: task_ExpDrvTask+48C
 797                  "MOV     R4, #1\n"          //@ Rd = Op2
 798                  "MOV     R0, R4\n"          //@ Rd = Op2
 799                  "MOV     R1, R4\n"          //@ Rd = Op2
 800                  "MOV     R2, R4\n"          //@ Rd = Op2
 801                  "MOV     R3, R4\n"          //@ Rd = Op2
 802                  "STR     R4, [SP]\n" //@ Store to Memory
 803                  "BL      sub_FF972804\n"    //@ Branch with Link
 804 
 805                  "MOV     R0, R4\n"          //@ Rd = Op2
 806                  "MOV     R1, R0\n"          //@ Rd = Op2
 807                  "MOV     R2, R0\n"          //@ Rd = Op2
 808                  "MOV     R3, R0\n"          //@ Rd = Op2
 809                  "STR     R4, [SP]\n" //@ Store to Memory
 810                  "BL      sub_FF972A5C\n"    //@ Branch with Link
 811 
 812 
 813      "loc_FF976F74:\n"                           //@ CODE XREF: task_ExpDrvTask+47C
 814                  "LDR     R2, =0x2E4F4\n"  //@ Load from Memory
 815                  "MOV     R3, #0\n"          //@ Rd = Op2
 816                  "LDR     R0, [SP,#0x4]\n" //@ Load from Memory
 817                  "STR     R3, [R2]\n"        //@ Store to Memory
 818                  "BL      sub_FF9722A8\n"    //@ Branch with Link
 819 
 820 
 821      "loc_FF976F88:\n"                           //@ CODE XREF: task_ExpDrvTask+C
 822                  "LDR     R3, =0x2E49C\n"  //@ Load from Memory
 823                  "MOV     R2, #0\n"          //@ Rd = Op2
 824                  "LDR     R0, [R3]\n"        //@ Load from Memory
 825                  "MOV     R1, R7\n"          //@ Rd = Op2
 826 //                 "BL      ReceiveMessageQueue\n" //@ Branch with Link
 827                  "BL      sub_FFB223A8\n" //@ Branch with Link
 828 
 829                  "LDR     R12, [SP,#0x4]\n" //@ Load from Memory
 830                  "LDR     R2, [R12]\n"       //@ Load from Memory
 831                  "CMP     R2, #0x23\n" //  @ '#'  Set cond. codes on Op1 - Op2
 832                  "BNE     loc_FF976A88\n"    //@ Branch
 833 
 834                  "MOV     R0, R12\n"         //@ Rd = Op2
 835                  "BL      sub_FF9722A8\n"    //@ Branch with Link
 836 
 837                  "LDR     R3, =0x2E498\n"  //@ Load from Memory
 838                  "MOV     R1, #1\n"          //@ Rd = Op2
 839                  "LDR     R0, [R3]\n"        //@ Load from Memory
 840 //                 "BL      SetEventFlag\n"    //@ Branch with Link
 841                  "BL      sub_FFB21C90\n"    //@ Branch with Link
 842 
 843                  "BL      _ExitTask\n"       //@ Branch with Link
 844 
 845                  "ADD     SP, SP, #0x20\n"   //@ Rd = Op1 + Op2
 846                  "LDMFD   SP!, {R4-R8,PC}\n" //@ Load Block from Memory
 847 
 848 //               "RET\n"                     //@ Return from Subroutine
 849                  );
 850 }
 851 
 852 void __attribute__((naked,noinline)) sub_FF973980_my() {
 853     asm volatile(
 854 
 855      "sub_FF973980:\n"                           //@ CODE XREF: task_ExpDrvTask+2FC
 856                  "STMFD   SP!, {R4-R6,LR}\n" //@ Store Block to Memory
 857                  "LDR     R3, =0x2E498\n"  //@ Load from Memory
 858                  "MOV     R4, R0\n"          //@ Rd = Op2
 859                  "MOV     R1, #0x3E\n"   // @ '>' Rd = Op2
 860                  "LDR     R0, [R3]\n"        //@ Load from Memory
 861 //                 "BL      ClearEventFlag\n"  //@ Branch with Link
 862                  "BL      sub_FFB21E2C\n"  //@ Branch with Link
 863 
 864                  "MOV     R1, #0\n"          //@ Rd = Op2
 865                  "LDRSH   R0, [R4,#4]\n"     //@ Load from Memory
 866                  "BL      sub_FF9723DC\n"    //@ Branch with Link
 867 
 868                  "MOV     R6, R0\n"          //@ Rd = Op2
 869                  "LDRSH   R0, [R4,#6]\n"     //@ Load from Memory
 870                  "BL      sub_FF972544\n"    //@ Branch with Link
 871 
 872                  "LDRSH   R0, [R4,#8]\n"     //@ Load from Memory
 873                  "BL      sub_FF9725E0\n"    //@ Branch with Link
 874 
 875                  "LDRSH   R0, [R4,#0xA]\n"   //@ Load from Memory
 876                  "BL      sub_FF97267C\n"    //@ Branch with Link
 877 
 878                  "LDRSH   R0, [R4,#0xC]\n"   //@ Load from Memory
 879                  "BL      sub_FF972718\n"    //@ Branch with Link
 880 
 881                  "LDR     R3, [R4]\n"        //@ Load from Memory
 882                  "CMP     R3, #9\n"          //@ Set cond. codes on Op1 - Op2
 883                  "MOV     R5, R0\n"          //@ Rd = Op2
 884                  "MOVEQ   R5, #0\n"          //@ Rd = Op2
 885                  "MOVEQ   R6, R5\n"          //@ Rd = Op2
 886                  "CMP     R6, #1\n"          //@ Set cond. codes on Op1 - Op2
 887                  "BNE     loc_FF973A04\n"    //@ Branch
 888 
 889                  "MOV     R2, #2\n"          //@ Rd = Op2
 890                  "LDRSH   R0, [R4,#4]\n"     //@ Load from Memory
 891 //                 "LDR     R1, =loc_FF9722FC\n" //@ Load from Memory
 892                  "LDR     R1, =0xFF9722FC\n" //@ Load from Memory
 893                  "BL      sub_FFAE28F8\n"    //@ Branch with Link
 894 
 895                  "LDR     R2, =0x2E4E8\n"  //@ Load from Memory
 896                  "MOV     R3, #0\n"          //@ Rd = Op2
 897                  "STR     R3, [R2]\n"        //@ Store to Memory
 898                  "B       loc_FF973A08\n"    //@ Branch
 899 
 900 
 901      "loc_FF973A04:\n"                           //@ CODE XREF: sub_FF973980+60
 902                  "BL      sub_FF9727B4\n"    //@ Branch with Link
 903 
 904 
 905      "loc_FF973A08:\n"                           //@ CODE XREF: sub_FF973980+80
 906                  "STRH    R0, [R4,#4]\n"     //@ Store to Memory
 907                  "CMP     R5, #1\n"          //@ Set cond. codes on Op1 - Op2
 908                  "BNE     loc_FF973A28\n"    //@ Branch
 909 
 910                  "LDRSH   R0, [R4,#0xC]\n"   //@ Load from Memory
 911 //                 "LDR     R1, =loc_FF9723C0\n" //@ Load from Memory
 912                  "LDR     R1, =0xFF9723C0\n" //@ Load from Memory
 913                  "MOV     R2, #0x20\n" //  @ ' ' @ Rd = Op2
 914                  "BL      sub_FF972BA8\n"    //@ Branch with Link
 915 
 916                  "B       loc_FF973A2C\n"    //@ Branch
 917 
 918      "loc_FF973A28:\n"                           //@ CODE XREF: sub_FF973980+90
 919                  "BL      sub_FF9727F4\n"    //@ Branch with Link
 920 
 921      "loc_FF973A2C:\n"                           //@ CODE XREF: sub_FF973980+A4
 922                  "STRH    R0, [R4,#0xC]\n"   //@ Store to Memory
 923                  "LDRSH   R0, [R4,#6]\n"     //@ Load from Memory
 924                  "BL      sub_FF93BD38_my\n"    //@ Branch with Link // again an ewvar copy of a function which we also are going to replace
 925 
 926                  "LDRSH   R0, [R4,#8]\n"     //@ Load from Memory
 927                  "MOV     R1, #1\n"          //@ Rd = Op2
 928                  "BL      sub_FF93DFEC\n"    //@ Branch with Link
 929 
 930                  "ADD     R0, R4, #8\n"      //@ Rd = Op1 + Op2
 931                  "MOV     R1, #0\n"          //@ Rd = Op2
 932                  "BL      sub_FF93E0AC\n"    //@ Branch with Link
 933 
 934                  "LDRSH   R0, [R4,#0xE]\n"   //@ Load from Memory
 935                  "BL      sub_FF9605D0\n"    //@ Branch with Link
 936 
 937                  "CMP     R6, #1\n"          //@ Set cond. codes on Op1 - Op2
 938                  "BNE     loc_FF973A90\n"    //@ Branch
 939 
 940                  "LDR     R3, =0x2E498\n"  //@ Load from Memory
 941                  "MOV     R2, #0xBB0\n"      //@ Rd = Op2
 942                  "LDR     R0, [R3]\n"        //@ Load from Memory
 943                  "MOV     R1, #2\n"          //@ Rd = Op2
 944                  "ADD     R2, R2, #8\n"      //@ Rd = Op1 + Op2
 945 //                 "BL      unknown_libname_854\n" //@ "Canon A-Series Firmware"
 946                  "BL      sub_FFB21C80\n" //@ "Canon A-Series Firmware"
 947 
 948                  "TST     R0, #1\n"          //@ Set cond. codes on Op1 & Op2
 949                  "BEQ     loc_FF973A90\n"    //@ Branch
 950 
 951                  "MOV     R1, #0x500\n"      //@ Rd = Op2
 952 //                 "LDR     R0, =aExpdrv_c\n"  //@ Load from Memory
 953                  "LDR     R0, =0xFF972254\n"  //@ Load from Memory => string "ExpDrv.c"
 954                  "ADD     R1, R1, #8\n"      //@ Rd = Op1 + Op2
 955 //                 "BL      DebugAssert\n"     //@ Branch with Link
 956                  "BL      sub_FFB2F4F0\n"     //@ Branch with Link
 957 
 958 
 959      "loc_FF973A90:\n"                           //@ CODE XREF: sub_FF973980+DC
 960                  "CMP     R5, #1\n"          //@ Set cond. codes on Op1 - Op2
 961                  "LDMNEFD SP!, {R4-R6,PC}\n" //@ Load Block from Memory
 962                  "LDR     R3, =0x2E498\n"  //@ Load from Memory
 963                  "MOV     R2, #0xBB0\n"      //@ Rd = Op2
 964                  "LDR     R0, [R3]\n"        //@ Load from Memory
 965                  "MOV     R1, #0x20\n"       // @ ' '\n" //@ Rd = Op2
 966                  "ADD     R2, R2, #8\n"      //@ Rd = Op1 + Op2
 967 //                 "BL      unknown_libname_854\n" //@ "Canon A-Series Firmware"
 968                  "BL      sub_FFB21C80\n" //@ "Canon A-Series Firmware"
 969 
 970                  "TST     R0, #1\n"          //@ Set cond. codes on Op1 & Op2
 971                  "LDMEQFD SP!, {R4-R6,PC}\n" //@ Load Block from Memory
 972                  "MOV     R1, #0x500\n"      //@ Rd = Op2
 973 //                 "LDR     R0, =aExpdrv_c\n"  //@ Load from Memory
 974                  "LDR     R0, =0xFF972254\n"  //@ Load from Memory
 975                  "ADD     R1, R1, #0xD\n"    //@ Rd = Op1 + Op2
 976                  "LDMFD   SP!, {R4-R6,LR}\n" //@ Load Block from Memory
 977 //                 "B       DebugAssert\n"     //@ Branch
 978                  "B       sub_FFB2F4F0\n"     //@ Branch with Link
 979 
 980             );
 981 }
 982 
 983 void __attribute__((naked,noinline)) sub_FF93BD38_my(){
 984 asm volatile(
 985 
 986 
 987      "sub_FF93BD38:\n"                           //@ CODE XREF: sub_FF93D684+Cp
 988                  "STMFD   SP!, {R4,LR}\n"    //@ Store Block to Memory
 989 //                 "LDR     R3, =unk_6544\n"   //@ Load from Memory
 990                  "LDR     R3, =0x6544\n"   //@ Load from Memory
 991                  "LDR     R2, [R3]\n"        //@ Load from Memory
 992                  "MOV     R1, #0x168\n"      //@ Rd = Op2
 993                  "MOV     R3, R0,LSL#16\n"   //@ Rd = Op2
 994                  "CMP     R2, #1\n"          //@ Set cond. codes on Op1 - Op2
 995                  "ADD     R1, R1, #3\n"      //@ Rd = Op1 + Op2
 996 //                 "LDR     R0, =aShutter_c\n" //@ Load from Memory => string "Shutter.c"
 997                  "LDR     R0, =0xFF93B554\n" //@ Load from Memory
 998                  "MOV     R4, R3,ASR#16\n"   //@ Rd = Op2
 999                  "BEQ     loc_FF93BD64\n"    //@ Branch
1000 
1001   //               "BL      DebugAssert\n"     //@ Branch with Link
1002                  "BL      sub_FFB2F4F0\n"     //@ Branch with Link
1003 
1004 
1005      "loc_FF93BD64:\n"                           //@ CODE XREF: sub_FF93BD38+24j
1006                  "MOV     R1, #0x170\n"      //@ Rd = Op2
1007                  "CMN     R4, #0xC00\n"      //@ Set cond. codes on Op1 + Op2
1008 //                 "LDR     R3, =unk_15036\n"  //@ Load from Memory
1009                  "LDR     R3, =0x15036\n"  //@ Load from Memory
1010   //               "LDR     R0, =aShutter_c\n" //@ Load from Memory
1011                  "LDR     R0, =0xFF93B554\n" //@ Load from Memory
1012                  "ADD     R1, R1, #1\n"      //@ Rd = Op1 + Op2
1013                  "LDREQSH R4, [R3]\n"        //@ Load from Memory
1014                  "LDRNE   R3, =0x15036\n"  //@ Load from Memory
1015                  "CMN     R4, #0xC00\n"      //@ Set cond. codes on Op1 + Op2
1016                  "STRH    R4, [R3]\n"        //@ Store to Memory
1017                  "BNE     loc_FF93BD90\n"    //@ Branch
1018 
1019 //                 "BL      DebugAssert\n"     //@ Branch with Link
1020                  "BL      sub_FFB2F4F0\n"     //@ Branch with Link
1021 
1022 
1023      "loc_FF93BD90:\n"                           //@ CODE XREF: sub_FF93BD38+50j
1024                  "MOV     R0, R4\n"          //@ Rd = Op2
1025 //                 "BL      sub_FF93CE88\n"    //@ Branch with Link
1026                  "BL      apex2us\n"    //@ Branch with Link => yet another function we need to make our way through to get to our own version
1027 
1028                  "MOV     R4, R0\n"          //@ Rd = Op2
1029 //                 "BL      nullsub_118\n"     //@ Branch with Link
1030                  "BL      sub_FF9C2BB0\n"     //@ Branch with Link
1031 
1032                  "MOV     R0, R4\n"          //@ Rd = Op2
1033                  "BL      sub_FF9DE41C\n"    //@ Branch with Link
1034 
1035                  "MOV     R1, #0x174\n"      //@ Rd = Op2
1036                  "TST     R0, #1\n"          //@ Set cond. codes on Op1 & Op2
1037                  "ADD     R1, R1, #2\n"      //@ Rd = Op1 + Op2
1038 //                 "LDR     R0, =aShutter_c\n" //@ Load from Memory
1039                  "LDR     R0, =0xFF93B554\n" //@ Load from Memory
1040                  "LDMEQFD SP!, {R4,PC}\n"    //@ Load Block from Memory
1041                  "LDMFD   SP!, {R4,LR}\n"    //@ Load Block from Memory
1042     //             "B       DebugAssert\n"     //@ Branch
1043                  "B       sub_FFB2F4F0\n"     //@ Branch with Link
1044         );
1045 }

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