reg 127 core/gps.c georegInit (t_georeg* reg, int size, t_regression_xy * buffer1, t_regression_xy * buffer2) { reg 128 core/gps.c regressionInit (®->lat_w, size, buffer1); reg 129 core/gps.c regressionInit (®->lon_w, size, buffer2); reg 133 core/gps.c georegAdd (t_georeg* reg, double time, t_geo* geo) { reg 134 core/gps.c regressionAdd (®->lat_w, time, geo->lat_w); reg 135 core/gps.c regressionAdd (®->lon_w, time, geo->lon_w); reg 139 core/gps.c georegActual (t_georeg* reg, t_geo* geo) { reg 140 core/gps.c geo->lat_w = regressionActual (®->lat_w); reg 141 core/gps.c geo->lon_w = regressionActual (®->lon_w); reg 145 core/gps.c georegChange (t_georeg* reg, t_geo* geo) { reg 146 core/gps.c geo->lat_w = regressionChange (®->lat_w); reg 147 core/gps.c geo->lon_w = regressionChange (®->lon_w); reg 131 lib/lua/lcode.c static int patchtestreg (FuncState *fs, int node, int reg) { reg 135 lib/lua/lcode.c if (reg != NO_REG && reg != GETARG_B(*i)) reg 136 lib/lua/lcode.c SETARG_A(*i, reg); reg 150 lib/lua/lcode.c static void patchlistaux (FuncState *fs, int list, int vtarget, int reg, reg 154 lib/lua/lcode.c if (patchtestreg(fs, list, reg)) reg 215 lib/lua/lcode.c static void freereg (FuncState *fs, int reg) { reg 216 lib/lua/lcode.c if (!ISK(reg) && reg >= fs->nactvar) { reg 218 lib/lua/lcode.c lua_assert(reg == fs->freereg); reg 343 lib/lua/lcode.c static void discharge2reg (FuncState *fs, expdesc *e, int reg) { reg 347 lib/lua/lcode.c luaK_nil(fs, reg, 1); reg 351 lib/lua/lcode.c luaK_codeABC(fs, OP_LOADBOOL, reg, e->k == VTRUE, 0); reg 355 lib/lua/lcode.c luaK_codeABx(fs, OP_LOADK, reg, e->u.s.info); reg 359 lib/lua/lcode.c luaK_codeABx(fs, OP_LOADK, reg, luaK_numberK(fs, e->u.nval)); reg 364 lib/lua/lcode.c SETARG_A(*pc, reg); reg 368 lib/lua/lcode.c if (reg != e->u.s.info) reg 369 lib/lua/lcode.c luaK_codeABC(fs, OP_MOVE, reg, e->u.s.info, 0); reg 377 lib/lua/lcode.c e->u.s.info = reg; reg 390 lib/lua/lcode.c static void exp2reg (FuncState *fs, expdesc *e, int reg) { reg 391 lib/lua/lcode.c discharge2reg(fs, e, reg); reg 400 lib/lua/lcode.c p_f = code_label(fs, reg, 0, 1); reg 401 lib/lua/lcode.c p_t = code_label(fs, reg, 1, 0); reg 405 lib/lua/lcode.c patchlistaux(fs, e->f, final, reg, p_f); reg 406 lib/lua/lcode.c patchlistaux(fs, e->t, final, reg, p_t); reg 409 lib/lua/lcode.c e->u.s.info = reg; reg 272 lib/lua/ldebug.c #define checkreg(pt,reg) check((reg) < (pt)->maxstacksize) reg 317 lib/lua/ldebug.c static Instruction symbexec (const Proto *pt, int lastpc, int reg) { reg 367 lib/lua/ldebug.c if (a == reg) last = pc; /* change register `a' */ reg 383 lib/lua/ldebug.c if (a <= reg && reg <= b) reg 399 lib/lua/ldebug.c if (reg == a+1) last = pc; reg 409 lib/lua/ldebug.c if (reg >= a+2) last = pc; /* affect all regs above its base */ reg 419 lib/lua/ldebug.c if (reg != NO_REG && pc < dest && dest <= lastpc) reg 434 lib/lua/ldebug.c if (reg >= a) last = pc; /* affect all registers above base */ reg 459 lib/lua/ldebug.c if (reg != NO_REG) /* tracing? */ reg 298 lib/lua/loadlib.c void **reg = ll_register(L, path); reg 299 lib/lua/loadlib.c if (*reg == NULL) *reg = ll_load(L, path); reg 300 lib/lua/loadlib.c if (*reg == NULL) reg 303 lib/lua/loadlib.c lua_CFunction f = ll_sym(L, *reg, sym); reg 268 lib/lua/lparser.c int reg = fs->freereg; reg 270 lib/lua/lparser.c luaK_nil(fs, reg, extra); reg 446 lib/lua/lparser.c int reg = ls->fs->freereg; reg 460 lib/lua/lparser.c fs->freereg = reg; /* free registers */ reg 257 tools/capdis.c const char *reg=cs_reg_name(handle,insn->detail->arm.operands[i].mem.base); reg 258 tools/capdis.c if(reg) { reg 259 tools/capdis.c printf(" base=%s",reg); reg 261 tools/capdis.c reg=cs_reg_name(handle,insn->detail->arm.operands[i].mem.index); reg 262 tools/capdis.c if(reg) { reg 263 tools/capdis.c printf(" index=%s",reg); reg 273 tools/capdis.c printf(" %s",cs_reg_name(handle,insn->detail->arm.operands[i].reg)); reg 467 tools/capdis.c sprintf(op_pfx,"%s, ",cs_reg_name(is->cs_handle,is->insn->detail->arm.operands[0].reg)); reg 598 tools/capdis.c cs_reg_name(is->cs_handle,insn->detail->arm.operands[0].reg), reg 619 tools/capdis.c cs_reg_name(is->cs_handle,insn->detail->arm.operands[0].reg), reg 625 tools/capdis.c cs_reg_name(is->cs_handle,insn->detail->arm.operands[0].reg), reg 631 tools/capdis.c cs_reg_name(is->cs_handle,insn->detail->arm.operands[0].reg), reg 641 tools/capdis.c cs_reg_name(is->cs_handle,insn->detail->arm.operands[0].reg), reg 1263 tools/chdk_dasm.c op = reg(op, 'p', instr>>8); reg 1267 tools/chdk_dasm.c op = reg(op, 'c', instr >> (4*(c-1))); reg 4860 tools/finsig_dryos.c int reg = -1; reg 4895 tools/finsig_dryos.c reg = fwRn(fw,k3+k4); reg 4899 tools/finsig_dryos.c if (reg>=0 && isLDR_cond(fw,k3+k4) && fwRd(fw,k3+k4)==reg) reg 4962 tools/finsig_dryos.c uint32_t reg = fw->buf[k+fbd[f][2]] & 0x000F0000; // Index register used reg 4964 tools/finsig_dryos.c if (((fw->buf[k+fbd[f][0]] & 0x0000F000) << 4) == reg) { ka = k+fbd[f][0]; } reg 4965 tools/finsig_dryos.c else if (((fw->buf[k+fbd[f][1]] & 0x0000F000) << 4) == reg) { ka = k+fbd[f][1]; } reg 4971 tools/finsig_dryos.c if (isSTR(fw,k1) && ((fw->buf[k1] & 0x000F0000) == reg)) reg 5677 tools/finsig_dryos.c uint32_t reg = (fwval(fw,k1+1) & 0x0000F000) >> 12; reg 5682 tools/finsig_dryos.c if (isLDR_PC(fw,k2) && isLDR(fw,k2+1) && (((fwval(fw,k2+1) & 0x000F0000) >> 16) == reg)) reg 5880 tools/finsig_dryos.c uint32_t reg = (fw->buf[k-1] & 0x000F0000) >> 16; reg 5881 tools/finsig_dryos.c uint32_t ldr_inst = 0xE51F0000 | (reg << 12); reg 6039 tools/finsig_dryos.c int reg = fwval(fw,k-1) & 0xF; reg 6042 tools/finsig_dryos.c if (isLDR(fw,k1) && (fwRd(fw,k1) == reg)) reg 6097 tools/finsig_dryos.c int reg = fwRn(fw,k1+1); reg 6101 tools/finsig_dryos.c if (isLDR_PC(fw,k2) && (fwRd(fw,k2) == reg)) reg 6303 tools/finsig_dryos.c int reg; // register used to assemble the address reg 6353 tools/finsig_dryos.c leds[j3].reg = fwRd(fw,k1+j2); reg 6383 tools/finsig_dryos.c leds[j3].reg = repeatreg; reg 6399 tools/finsig_dryos.c if ((leds[j3].reg == fwRd(fw,k1+j2)) && (leds[j3].addr == LDR2val(fw,k1+j2))) reg 6408 tools/finsig_dryos.c if (leds[j3].reg == fwRd(fw,k1+j2)) reg 6426 tools/finsig_dryos.c if (leds[j3].reg == fwRd(fw,k1+j2)) reg 6431 tools/finsig_dryos.c else if (leds[j3].reg == fwRn(fw,k1+j2)) reg 6444 tools/finsig_dryos.c if (leds[j3].reg == fwRd(fw,k1+j2)) reg 6449 tools/finsig_dryos.c else if (leds[j3].reg == fwRn(fw,k1+j2)) reg 6464 tools/finsig_dryos.c if (leds[j3].reg == fwRd(fw,k1+j2)) reg 6470 tools/finsig_dryos.c else if (isMOV_immed(fw,k1+j2) && (leds[j3].reg == fwRd(fw,k1+j2))) reg 7274 tools/finsig_dryos.c int reg; reg 7289 tools/finsig_dryos.c key_info[kcount].reg = r; reg 7329 tools/finsig_dryos.c if (p1->reg > p2->reg) reg 7333 tools/finsig_dryos.c else if (p1->reg < p2->reg) reg 7392 tools/finsig_dryos.c bprintf("// { %d, %-20s,0x%08x }, // Found @0x%08x, levent 0x%02x%s\n",key_info[k].reg,key_info[k].nm,key_info[k].bits,key_info[k].fadr,key_info[k].ev,(key_info[k].inv==0)?"":" (uses inverted logic in physw_status)"); reg 7901 tools/finsig_dryos.c uint32_t findTaskAddress(firmware *fw, int k, int reg) reg 7907 tools/finsig_dryos.c if (isLDR_PC(fw,k+o) && (fwRd(fw,k+o) == reg)) reg 7913 tools/finsig_dryos.c if (fwval(fw,k+i) == (0xE5900000 | (reg << 12) | (reg << 16))) // LDR Rx,[Rx] reg 7920 tools/finsig_dryos.c else if (isADR_PC(fw,k+o) && (fwRd(fw,k+o) == reg)) reg 1031 tools/finsig_thumb2.c if(is->insn->detail->arm.operands[0].reg == ARM_REG_R0) { reg 1088 tools/finsig_thumb2.c if(is->insn->detail->arm.operands[0].reg != ARM_REG_R0) { reg 1142 tools/finsig_thumb2.c if(is->insn->detail->arm.operands[0].reg != ARM_REG_R0) { reg 1185 tools/finsig_thumb2.c if(is->insn->detail->arm.operands[0].reg != ARM_REG_R0) { reg 1275 tools/finsig_thumb2.c if(is->insn->detail->arm.operands[0].reg == ARM_REG_R0) { reg 1507 tools/finsig_thumb2.c uint32_t reg=is->insn->detail->arm.operands[0].reg; reg 1515 tools/finsig_thumb2.c if(is->insn->detail->arm.operands[1].mem.base != reg) { reg 1717 tools/finsig_thumb2.c || is->insn->detail->arm.operands[0].reg != ARM_REG_R0) { reg 1888 tools/finsig_thumb2.c && insn->detail->arm.operands[0].reg == ARM_REG_R0 reg 1893 tools/finsig_thumb2.c if(ptr_reg == ARM_REG_INVALID || !isLDR_PC(insn) || (arm_reg)insn->detail->arm.operands[0].reg != ptr_reg) { reg 1964 tools/finsig_thumb2.c if(is->insn->detail->arm.operands[0].reg == ARM_REG_R0) { reg 2319 tools/finsig_thumb2.c if(fw->is->insn->id == ARM_INS_PUSH && fw->is->insn->detail->arm.operands[0].reg == ARM_REG_R0) { reg 3156 tools/finsig_thumb2.c if((arm_reg)is->insn->detail->arm.operands[1].reg == desc.reg_base) { reg 3245 tools/finsig_thumb2.c if (!(isLDR_PC(fw->is->insn) && fw->is->insn->detail->arm.operands[0].reg == ARM_REG_R0)) { reg 3256 tools/finsig_thumb2.c if (is->insn->id == ARM_INS_PUSH && is->insn->detail->arm.operands[0].reg == ARM_REG_R4) { reg 3285 tools/finsig_thumb2.c if (fw->is->insn->id == ARM_INS_PUSH && fw->is->insn->detail->arm.operands[0].reg == ARM_REG_R4) { reg 3290 tools/finsig_thumb2.c if (isLDR_PC(fw->is->insn) && fw->is->insn->detail->arm.operands[0].reg == ARM_REG_R0) { reg 3939 tools/finsig_thumb2.c if(is->insn->detail->arm.operands[0].reg != ARM_REG_R0) { reg 4207 tools/finsig_thumb2.c arm_reg rb=is->insn->detail->arm.operands[0].reg; reg 4220 tools/finsig_thumb2.c || is->insn->detail->arm.operands[0].reg != ARM_REG_R0 reg 4252 tools/finsig_thumb2.c arm_reg rb=is->insn->detail->arm.operands[0].reg; reg 4447 tools/finsig_thumb2.c arm_reg reg_base = is->insn->detail->arm.operands[0].reg; // reg value was loaded into reg 4454 tools/finsig_thumb2.c if((arm_reg)is->insn->detail->arm.operands[0].reg != reg_base) { reg 4468 tools/finsig_thumb2.c if(is->insn->id != ARM_INS_STR || (arm_reg)is->insn->detail->arm.operands[1].reg != reg_base) { reg 4649 tools/finsig_thumb2.c if(is->insn->detail->arm.operands[0].reg != ARM_REG_R0) { reg 4708 tools/finsig_thumb2.c arm_reg ptr_reg = is->insn->detail->arm.operands[0].reg; reg 4830 tools/finsig_thumb2.c if(is->insn->detail->arm.operands[0].reg != ARM_REG_R0) { reg 4930 tools/finsig_thumb2.c arm_reg reg = ARM_REG_R0 + (rule->param & SIG_STRCALL_ARG_MASK); reg 4939 tools/finsig_thumb2.c uint32_t call_adr = find_const_ref_call(fw, is, SEARCH_NEAR_REF_RANGE*2, 8, reg, str_adr); reg 5677 tools/finsig_thumb2.c ar = is->insn->detail->arm.operands[0].reg; reg 5687 tools/finsig_thumb2.c if (is->insn->id == ARM_INS_ADD && is->insn->detail->arm.operands[1].reg == ar) { reg 5842 tools/finsig_thumb2.c if(insn->detail->arm.operands[0].reg != ARM_REG_R0 reg 5866 tools/finsig_thumb2.c if((arm_reg)insn->detail->arm.operands[0].reg != ptr_reg) { reg 6398 tools/finsig_thumb2.c int reg; reg 6411 tools/finsig_thumb2.c vals->reg=(info >>5) & 7; reg 6433 tools/finsig_thumb2.c if(v.raw_info == 0 || v.raw_info == 0xFFFFFFFF || v.reg > 2) { reg 6453 tools/finsig_thumb2.c fprintf(f,"0x%08x 0x%08x 0x%08x %-5d 0x%08x %d\n",tadr,v.raw_info,v.ev,v.reg,v.bit,v.no_invert); reg 6471 tools/finsig_thumb2.c bprintf("//#define %-20s%d\n",rn,v.reg); reg 6477 tools/finsig_thumb2.c int reg; reg 6492 tools/finsig_thumb2.c key_info[kcount].reg = r; reg 6512 tools/finsig_thumb2.c add_kinfo(v.reg,v.bit|xtra,name,adr,v.ev,(v.no_invert)?0:1); reg 6518 tools/finsig_thumb2.c if (p1->reg > p2->reg) reg 6522 tools/finsig_thumb2.c else if (p1->reg < p2->reg) reg 6581 tools/finsig_thumb2.c bprintf("// { %d, %-20s,0x%08x }, // Found @0x%08x, levent 0x%02x%s\n",key_info[k].reg,key_info[k].nm,key_info[k].bits,key_info[k].fadr,key_info[k].ev,(key_info[k].inv==0)?"":" (uses inverted logic in physw_status)"); reg 3906 tools/finsig_vxworks.c int reg = -1; reg 3941 tools/finsig_vxworks.c reg = fwRn(fw,k3+k4); reg 3945 tools/finsig_vxworks.c if (reg>=0 && isLDR_cond(fw,k3+k4) && fwRd(fw,k3+k4)==reg) reg 4706 tools/finsig_vxworks.c uint32_t reg = (fwval(fw,k1+1) & 0x0000F000) >> 12; reg 4711 tools/finsig_vxworks.c if (isLDR_PC(fw,k2) && isLDR(fw,k2+1) && (((fwval(fw,k2+1) & 0x000F0000) >> 16) == reg)) reg 4814 tools/finsig_vxworks.c int reg = -1; reg 4818 tools/finsig_vxworks.c if (reg < 0 && isLDR_PC(fw,k1)) reg 4830 tools/finsig_vxworks.c reg = fwRd(fw,k1); reg 4834 tools/finsig_vxworks.c if (reg<0) reg 4836 tools/finsig_vxworks.c if ((fwval(fw,k1)&0xfffff000) == (0xe2800000+(reg<<12)+(reg<<16))) // ADD Rx, Rx, #imm reg 5355 tools/finsig_vxworks.c int reg; // register used to assemble the address reg 5388 tools/finsig_vxworks.c led.reg = fwRd(fw,j1); reg 5394 tools/finsig_vxworks.c if ((fwval(fw,n)&0xfffff000) == (0xe2800000+(led.reg<<12)+(led.reg<<16))) // ADD Rx, Rx, #0xc00000yz reg 5401 tools/finsig_vxworks.c else if ((fwval(fw,n)&0xfffff000) == (0xe3a00000+(led.reg<<12))) // MOV Rx, #imm reg 5407 tools/finsig_vxworks.c if ((fwval(fw,m)&0xfff0f000) == (0xe5800000+(led.reg<<12))) // STR Rx, [Ry, imm] reg 5480 tools/finsig_vxworks.c int reg; reg 5495 tools/finsig_vxworks.c key_info[kcount].reg = r; reg 5535 tools/finsig_vxworks.c if (p1->reg > p2->reg) reg 5539 tools/finsig_vxworks.c else if (p1->reg < p2->reg) reg 5598 tools/finsig_vxworks.c bprintf("// { %d, %-20s,0x%08x }, // Found @0x%08x, levent 0x%02x%s\n",key_info[k].reg,key_info[k].nm,key_info[k].bits,key_info[k].fadr,key_info[k].ev,(key_info[k].inv==0)?"":" (uses inverted logic in physw_status)"); reg 6088 tools/finsig_vxworks.c int reg = fwRn(fw,k+o); reg 6093 tools/finsig_vxworks.c if (isMOV_immed(fw,k1) && (fwRd(fw,k1) == reg)) reg 6111 tools/finsig_vxworks.c int reg = fwRn(fw,k+o); reg 6116 tools/finsig_vxworks.c if (isMOV_immed(fw,k1) && (fwRd(fw,k1) == reg)) reg 510 tools/firmware_load_ng.c return (insn->detail->arm.operands[0].reg == ARM_REG_PC); reg 519 tools/firmware_load_ng.c && insn->detail->arm.operands[0].reg != ARM_REG_PC reg 521 tools/firmware_load_ng.c && insn->detail->arm.operands[1].reg == ARM_REG_PC reg 531 tools/firmware_load_ng.c && insn->detail->arm.operands[0].reg != ARM_REG_PC reg 533 tools/firmware_load_ng.c && insn->detail->arm.operands[1].reg == ARM_REG_PC reg 542 tools/firmware_load_ng.c && insn->detail->arm.operands[0].reg != ARM_REG_PC reg 544 tools/firmware_load_ng.c && insn->detail->arm.operands[1].reg == ARM_REG_PC reg 553 tools/firmware_load_ng.c && insn->detail->arm.operands[0].reg != ARM_REG_PC reg 555 tools/firmware_load_ng.c && insn->detail->arm.operands[1].reg == ARM_REG_PC reg 566 tools/firmware_load_ng.c && insn->detail->arm.operands[0].reg == ARM_REG_LR) { reg 577 tools/firmware_load_ng.c && insn->detail->arm.operands[i].reg == ARM_REG_PC) { reg 585 tools/firmware_load_ng.c && insn->detail->arm.operands[0].reg == ARM_REG_PC reg 587 tools/firmware_load_ng.c && insn->detail->arm.operands[1].reg == ARM_REG_LR) { reg 602 tools/firmware_load_ng.c && insn->detail->arm.operands[i].reg == ARM_REG_LR) { reg 618 tools/firmware_load_ng.c && insn->detail->arm.operands[i].reg == ARM_REG_LR) { reg 634 tools/firmware_load_ng.c && insn->detail->arm.operands[i].reg == ARM_REG_PC) { reg 837 tools/firmware_load_ng.c && insn->detail->arm.operands[0].reg == ARM_REG_PC) { reg 893 tools/firmware_load_ng.c if((arm_reg)fw->is->insn->detail->arm.operands[0].reg == i_reg reg 1372 tools/firmware_load_ng.c arm_reg rd = fw->is->insn->detail->arm.operands[0].reg; reg 1465 tools/firmware_load_ng.c && is_init->insn->detail->arm.operands[0].reg == ARM_REG_IP reg 1475 tools/firmware_load_ng.c && fw->is->insn->detail->arm.operands[0].reg == ARM_REG_IP reg 1490 tools/firmware_load_ng.c && fw->is->insn->detail->arm.operands[0].reg == ARM_REG_IP) { reg 1571 tools/firmware_load_ng.c r.reg_base=is->insn->detail->arm.operands[0].reg; reg 1590 tools/firmware_load_ng.c if((arm_reg)is->insn->detail->arm.operands[0].reg != r.reg_base) { reg 1616 tools/firmware_load_ng.c if(is->insn->id != ARM_INS_LDR || (arm_reg)is->insn->detail->arm.operands[1].reg != r.reg_base) { reg 1619 tools/firmware_load_ng.c if(is->insn->detail->arm.operands[0].type == ARM_OP_REG && (arm_reg)is->insn->detail->arm.operands[0].reg == r.reg_base) { reg 1625 tools/firmware_load_ng.c r.reg_val = is->insn->detail->arm.operands[0].reg; reg 1970 tools/firmware_load_ng.c if(!reg_in_range((arm_reg)insn->detail->arm.operands[i].reg, reg 1974 tools/firmware_load_ng.c } else if((arm_reg)insn->detail->arm.operands[i].reg != match->operands[i].reg1) { reg 2464 tools/firmware_load_ng.c ra = is->insn->detail->arm.operands[0].reg; reg 2468 tools/firmware_load_ng.c || is->insn->detail->arm.operands[0].reg != ra reg 2482 tools/firmware_load_ng.c rb = is->insn->detail->arm.operands[0].reg; reg 2486 tools/firmware_load_ng.c || is->insn->detail->arm.operands[0].reg != rb